AD1816AJS View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD1816AJS Datasheet PDF : 52 Pages
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AD1816A
SSPVI
SS/SB Playback Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for
SS/SB playback or (2) The AD1816A did not request data for SS/SB playback in the previous frame (see the
SSPRQ bit in the Status Word Output). Otherwise, setting this bit indicates that Slots 4 and 5 contain valid right
and left SS/SB playback substitution data. If in “capture rate equal to playback rate” mode, setting this bit also in-
dicates that valid capture substitution data is being sent to the AD1816A. If not in modem mode, right and left
channel capture substitution data is accepted in Slots 2 and 3 respectively. If in modem mode, only mono capture
substitution data is accepted in slots 2 and 3. When this bit is cleared, data in all slots controlled by this bit, as de-
fined above, is ignored.
SSCVI
SS/SB Capture Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for SS/
SB capture or (2) The AD1816A did not request data for SS/SB capture in the previous frame (see the SSCRQ
bit in the Status Word Output). Otherwise, setting this bit indicates that valid SS/SB capture substitution data is
being sent to the AD1816A. If not in modem mode, or DSP port or ISA bus based, right and left channel capture
data is accepted in Slots 2 and 3 respectively. If in modem mode, only mono capture substitution data is accepted
in Slot 3, because Slot 2, which is mapped to the right capture channel, is being used for modem. This mono data
will, however, be sent to both left and right ISA SS/SB capture channels. When this bit is cleared, data in Slots 3
and 2 is ignored.
RES
Reserved: To ensure future compatibility write “0” to all reserved bits.
FCLR
DSP Port Clear Status Flag. When this bit is set, (write 1), the PNPR and PDN flag bits in the status word (Bits
15 and 14 of slots 0 SDO) are cleared. When this bit is cleared, (writing a 0), it has no effect on PNPR and PDN
and preserves them in the previous states.
Status Word Output (Slot 0 SDO)
15
PDN
7
MB1
14
PNPR
6
MB0
13
12
11
10
9
8
RES
SSCVO
SSPVO
FMVO
IS1VO
IS0VO
5
4
3
2
1
0
RES
SSCRQ
SSPRQ
FMRQ
IS1RQ
IS0RQ
IS0RQ
IS1RQ
FMRQ
SSPRQ
SSCRQ
MB0
MB1
IS0VO
IS1V1
FMVO
SSPVO
SSCVO
I2S Port (0) Input Request Flag. This bit is set if intercept mode is enabled for I2S Port (0) and its four-word ste-
reo input buffer is not full.
I2S Port (1) Input Request Flag. This bit is set if intercept mode is enabled for I2S Port (1) and its four-word ste-
reo input buffer is not full.
FM Synthesis Input Request Flag. This bit is set if intercept mode is enabled for FM synthesis and its four-word
stereo input buffer is not full.
SS/SB Playback Input Request Flag. This bit is set if intercept mode is enabled for SS/SB playback and its four-
word stereo input buffer is not full.
SS/SB Capture Input Request Flag. This bit is set if intercept mode is enabled for SS/SB capture and its
four-word stereo input buffer is not full.
Mailbox 0 Status Flag. This bit is set if the most recent action to SS indirect register 42 (DSP port Mail Box 1)
was a write, and is cleared if the most recent action was a read. The status of this bit is also reflected in SS indirect
register 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and a
host CPU on the ISA bus.
Mailbox 1 Status Flag. This bit is set if the most recent action to SS indirect register 43 (DSP port Mail Box 1)
was a write and is cleared if the most recent action was a read. The status of this bit is also reflected in SS indirect
register 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and a
host CPU on the ISA bus.
I2S Port 0 Valid Out. This bit is set if Slots 10 and 11 contain valid right and left I2S Port 0 data.
I2S Port 1 Valid Out. This bit is set if Slots 8 and 9 contain valid right and left I2S Port 1 data.
FM Synthesis Valid Out. This bit is set if Slots 6 and 7 contain valid left and right FM synthesis data.
SS/SB Playback Valid Out. This bit is set if Slots 4 and 5 contain valid right and left SS/SB playback data.
SS/SB Capture Valid Out. This bit is set if valid SS/SB capture data is being transmitted. If not in a modem mode,
Slots 2 and 3 will contain valid right and left SS/SB capture data. If in modem mode, only Slot 3 will contain valid
left SS/SB capture data as Slot 2 and the ADC right channel are used by the modem.
REV. A
–19–
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