GAL16LV8C-10LJ View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

GAL16LV8C-10LJ

Low Voltage E2CMOS PLD eneric Array Logic™

Lattice Semiconductor 

fmax Descriptions

CLK

Specifications GAL16LV8

LOGIC

ARRAY

REGISTER

ts u

tc o

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from measured

tsu and tco.

CLK

LOGIC

ARRAY

REGISTER

tsu + th

fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This

is to allow for a clock duty cycle of other than 50%.

LOGIC

ARRAY

CLK

REGISTER

t cf

t pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by subtracting tsu from

the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The

value of tcf is used primarily when calculating the delay from

clocking a register to a combinatorial output (through registered

feedback), as shown above. For example, the timing from clock

to a combinatorial output is equal to tcf + tpd.

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