Clock operation
M41T00CAP
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency. The FT/OUT pin is an open drain output which requires a
pull-up resistor to VCC for proper operation. A 500-10 kΩ resistor is recommended in order
to control the rise time. The FT bit is cleared on power-down.
Figure 10. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
ΔF
F
=
K
x
(T
–
TO)2
K = –0.036 ppm/°C2 ± 0.006 ppm/°C2
TO = 25°C ± 5°C
–140
–160
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80
Temperature °C
AI07888
Figure 11. Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
4.3
Century bit
Bits D7 and D6 of clock register 02h contain the century enable bit (CEB) and the century bit
(CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at
the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not
toggle.
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Doc ID 14557 Rev 5