PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS
Param
No.
Symbol
Characteristics
Min
Typ
150
151
153
154
156
157
157A
166
171
171A
TADV2ALL Address Out Valid to ALE (address setup time) 0.25 TCY – 10 —
TALL2ADL ALE to Address Out Invalid (address hold time)
5
—
TWRH2ADL WRn to Data Out Invalid (data hold time)
5
—
TWRL
WRn Pulse Width
0.5 TCY – 5 0.5 TCY
TADV2WRH Data Valid before WRn (data setup time)
0.5 TCY – 10 —
TBSV2WRL Byte Select Valid before WRn (byte select setup
0.25 TCY
—
time)
TWRH2BSI WRn to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 —
TALH2ALH ALE to ALE (cycle time)
—
TCY
TALH2CSL Chip Enable Active to ALE
—
—
TUBL2OEH AD Valid to Chip Enable Active
0.25 TCY – 20 —
Max
—
—
—
—
—
—
—
—
10
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FIGURE 26-11:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
I/O Pins
Note: Refer to Figure 26-6 for load conditions.
30
31
34
34
DS39609C-page 324
2003-2013 Microchip Technology Inc.