PIC18F6520/8520/6620/8620/6720/8720
FIGURE 26-12: BROWN-OUT RESET TIMING
VDD
VIRVST
BVDD
35
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
VBGAP = 1.2V
TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL MCLR Pulse Width (low)
2
—
—
s
31
TWDT Watchdog Timer Time-out Period (no
7
18
33
ms
postscaler)
32
TOST
Oscillation Start-up Timer Period
1024 TOSC — 1024 TOSC — TOSC = OSC1 period
33
TPWRT Power-up Timer Period
28
72
132
ms
34
TIOZ
I/O High-Impedance from MCLR Low
—
2
—
s
or Watchdog Timer Reset
35
TBOR Brown-out Reset Pulse Width
200
—
—
s VDD BVDD (see D005)
36
TIVRST Time for Internal Reference
Voltage to become stable
—
20
50
s
37
TLVD
Low-Voltage Detect Pulse Width
200
—
—
s VDD VLVD
FIGURE 26-13: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
T1OSO/T13CKI
40
41
42
45
46
47
48
TMR0 or
TMR1
Note: Refer to Figure 26-6 for load conditions.
2003-2013 Microchip Technology Inc.
DS39609C-page 325