PIC18F8520-IPT301 View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F8520-IPT301
Microchip Technology
PIC18F8520-IPT301 Datasheet PDF : 380 Pages
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PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70 TSSL2SCH, SS to SCK or SCK Input
TSSL2SCL
TCY
—
71 TSCH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72 TSCL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
—
73A TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40 —
74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
—
75 TDOR
SDO Data Output Rise Time
PIC18FXX20
—
25
PIC18LFXX20
—
45
76 TDOF
SDO Data Output Fall Time
—
25
78 TSCR
SCK Output Rise Time
(Master mode)
PIC18FXX20
PIC18LFXX20
—
25
—
45
79 TSCF
SCK Output Fall Time (Master mode)
—
25
80 TSCH2DOV, SDO Data Output Valid after SCK PIC18FXX20
TSCL2DOV Edge
PIC18LFXX20
—
50
—
100
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
FIGURE 26-17: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
bit 6 - - - - - -1
75, 76
SDI
MSb In
bit 6 - - - -1
74
Note: Refer to Figure 26-6 for load conditions.
LSb
LSb In
2003-2013 Microchip Technology Inc.
DS39609C-page 329
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