ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10F269Z2QX Datasheet PDF : 161 Pages
| |||
ST10F269Z2Qx
The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins
P0.15-13 (P0H.7-5).
Figure 67 : Generation Mechanisms for the CPU Clock
Phase locked loop operation
fXTAL
fCPU
Direct Clock Drive
fXTAL
TCL TCL
fCPU
Prescaler Operation
fXTAL
TCL TCL
fCPU
TCL TCL
21.4.3 - Clock Generation Modes
The Table 34 associates the combinations of these three bits with the respective clock generation mode.
Table 34 : CPU Frequency Generation
P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F External Clock Input Range1
Notes
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
fXTAL x 4
fXTAL x 3
fXTAL x 2
fXTAL x 5
fXTAL x 1
fXTAL x 1.5
fXTAL x 0.5
fXTAL x 2.5
2.5 to 10MHz
3.33 to 13.33MHz
5 to 20MHz
2 to 8MHz
1 to 40MHz
6.66 to 26.66MHz
2 to 80MHz
4 to 16MHz
Default configuration
Direct drive2
CPU clock via prescaler3
Notes: 1. The external clock input range refers to a CPU clock range of 1...40MHz.
2. The maximum input frequency depends on the duty cycle of the external clock signal.
3. The maximum input frequency is 25MHz when using an external crystal with the internal oscillator; providing that internal serial
resistance of the crystal is less than 40Ω. However, higher frequencies can be applied with an external clock source on pin XTAL1,
but in this case, the input clock signal must reach the defined levels VIL and VIH2..
137/161
Share Link: 