ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics
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ST10F269Z2QX Datasheet PDF : 161 Pages
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ST10F269Z2Qx
The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes fCPU to keep it
locked on fXTAL. The relative deviation of TCL is
the maximum when it is referred to one TCL
period. It decreases according to the formula and
to the Figure 68 given below. For N periods of
TCL the minimum value is computed using the
corresponding deviation DN:
TCL M I N
=
T
C
LN
OM
×
1
–
--1-D---0--N-0----
DN= ±(4 – N ⁄ 15)[%]
Figure 68 : Approximated Maximum PLL Jitter
where N = number of consecutive TCL periods
and 1 ≤ N ≤ 40. So for a period of 3 TCL periods
(N = 3):
D3
= 4 - 3/15 = 3.8%
3TCLmin
= 3TCLNOM x (1 - 3.8/100)
= 3TCLNOM x 0.962
3TCLmin = 36.075ns (at fCPU = 40MHz)
This is especially important for bus cycles using wait
states and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer
periods (e.g. pulse train generation or measurement,
lower Baud rates, etc.) the deviation caused by the
PLL jitter is negligible.
Max.jitter [%]
±4
±3
±2
±1
This approximated formula is valid for
1 ≤ N ≤ 40 and 10MHz ≤ fCPU ≤ 40MHz.
24
8
16
32
N
21.4.8 - External Clock Drive XTAL1
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125 °C
Parameter
Symbol
fCPU = fXTAL
min
max
fCPU = fXTAL / 2
min
max
fCPU = fXTAL x F
F = 1.5/2,/2.5/3/4/5
min
max
Unit
Oscillator period
High time
Low time
Rise time
Fall time
tOSC SR 25 1
–
12.5
–
40 x N 100 x N
ns
t1 SR 10 2
–
52
–
10 2
–
ns
t2 SR 10 2
–
52
–
10 2
–
ns
t3 SR
–
32
–
32
–
32
ns
t4 SR
–
32
–
32
–
32
ns
Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25MHz is the maximum input
frequency when using an external crystal oscillator. However, 40MHz can be applied with an external clock source.
2. The input clock signal must reach the defined levels VIL and VIH2.
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