ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics
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ST10F269Z2QX Datasheet PDF : 161 Pages
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ST10F269Z2Qx
21.4.12 - CLKOUT and READY
VDD = 5V ± 10%, VSS = 0V, TA = -40 to + 125°C, CL = 50pF
Table 37 : CLKOUT and READY Characteristics
Symbol
Parameter
Maximum CPU Clock
= 40 MHz
Minimum Maximum
Variable CPU Clock
1/2TCL = 1 to 40 MHz
Minimum
Maximum
t29 CC CLKOUT cycle time
25
t30 CC CLKOUT high time
4
t31 CC CLKOUT low time
3
t32 CC CLKOUT rise time
–
t33 CC CLKOUT fall time
–
t34 CC CLKOUT rising edge to
ALE falling edge
-2 + tA
t35 SR Synchronous READY
setup time to CLKOUT
12.5
t36 SR Synchronous READY
2
hold time after CLKOUT
t37 SR Asynchronous READY
35
low time
t58 SR Asynchronous READY
setup time
12.5
1)
25
–
–
4
4
8 + tA
–
2TCL
TCL – 8.5
TCL – 9.5
–
–
-2 + tA
12.5
2TCL
ns
–
ns
–
ns
4
ns
4
ns
8 + tA
ns
–
ns
–
2
–
ns
–
2TCL + 10
–
ns
–
12.5
–
ns
t59 SR Asynchronous READY
2
–
2
–
ns
hold time
1)
t60 SR Async. READY hold time after
RD, WR high (Demultiplexed
0
0 + 2tA + tC + tF
2)
Bus)
2)
0
TCL - 12.5
ns
+ 2tA + tC + tF 2)
Notes: 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time
for deactivating READY.
The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
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