ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10F269Z2QX Datasheet PDF : 161 Pages
| |||
ST10F269Z2Qx
21.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing
21.4.14.1 Master Mode
VCC = 5V ±10%, VSS = 0V, CPU clock = 40MHz, TA = -40 to +125°C, CL = 50pF
Symbol
Parameter
Maximum Baud rate = 10M Baud Variable Baud rate
(<SSCBR> = 0001h)
(<SSCBR>=0001h-FFFFh) Unit
Minimum
Maximum
Minimum Maximum
t300 CC SSC clock cycle time
100
t301 CC SSC clock high time
40
t302 CC SSC clock low time
40
t303 CC SSC clock rise time
–
t304 CC SSC clock fall time
–
t305 CC Write data valid after shift edge
–
t306 CC Write data hold after shift edge 1
-2
t307p SR Read data setup time before
37.5
latch edge, phase error
detection on (SSCPEN = 1)
t308p SR Read data hold time after latch
50
edge, phase error detection on
(SSCPEN = 1)
t307 SR Read data setup time before
25
latch edge, phase error
detection off (SSCPEN = 0)
t308
SR Read data hold time after latch
edge, phase error detection off
0
(SSCPEN = 0)
100
8 TCL 262144 TCL ns
–
t300/2 - 10
–
ns
–
t300/2 - 10
–
ns
10
–
10
ns
10
–
10
ns
15
–
15
ns
–
-2
–
ns
–
2TCL+12.5
–
ns
–
4TCL
–
ns
–
2TCL
–
ns
–
0
–
ns
Note: 1. Timing guaranteed by design.
The formula for SSC Clock Cycle time is: t300 = 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.
Figure 81 : SSC Master Timing
SCLK
1)
t300
t305
t301
t302
2)
t304
t305
t303
t306
MTSR
1st Out Bit
2nd Out Bit
t305
Last Out Bit
MRST
t t 307 308
1st.In Bit
2nd.In Bit
t t 307 308
Last.In Bit
Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn
in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
157/161
Share Link: 