ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10F269Z2QX

16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM

STMicroelectronics 

ST10F269Z2Qx

21.4.13 - External Bus Arbitration

VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF

Symbol

Parameter

Maximum CPU Clock

= 40 MHz

Minimum Maximum

Variable CPU Clock

1/2TCL = 1 to 40 MHz

Minimum

Maximum

t61 SR HOLD input setup time

to CLKOUT

15

–

15

t62 CC CLKOUT to HLDA high

or BREQ low delay

–

12.5

–

t63 CC CLKOUT to HLDA low

or BREQ high delay

–

12.5

–

t64 CC CSx release

1

–

15

–

–

ns

12.5

ns

12.5

ns

15

ns

t65 CC CSx drive

-4

15

-4

t66 CC Other signals release

1

–

15

–

t67 CC Other signals drive

-4

15

-4

Note: 1. Partially tested, guaranteed by design characterization.

Figure 79 : External Bus Arbitration (Releasing the Bus)

15

ns

15

ns

15

ns

CLKOUT

t61

HOLD

t63

HLDA

BREQ

CSx

(P6.x)

Others

1)

t62

2)

t64 3)

t66

1)

Notes: 1. The ST10F269 will complete the currently running bus cycle before granting bus access.

2. This is the first possibility for BREQ to become active.

3. The CS outputs will be resistive high (pull-up) after t64.

155/161

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