ST20-GP1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST20-GP1 Datasheet PDF : 116 Pages
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ST20-GP1
the initial bus width of all banks after reset.
BootSource[1:0] Bootstrap start-up conditions
00
Boot from link. 16-bit bus width for all banks.
01
Boot from ROM. 8-bit bus width for all banks. Link operational.
10
Boot from ROM. 16-bit bus width for all banks. Link powered down.
11
Boot from ROM. 8-bit bus width for all banks. Link powered down.
Table 9.1 BootSource0-1 encoding
9.2 Strobe allocation
Pin
notMemCE0-3
notMemOE0-3
notMemWB0
notMemWB1
Bank allocation
1 per bank
1 per bank
Shared amongst
all banks.
Shared amongst
all banks.
Correspondence
0 ⇒ bank 0
1 ⇒ bank 1
2 ⇒ bank 2
3 ⇒ bank 3
0 ⇒ bank 0
1 ⇒ bank 1
2 ⇒ bank 2
3 ⇒ bank 3
MemData0-7
Active access type
Reads and writes
Reads only
Writes only. Indicates valid write data on MemData0-7.
16-bit bus:
MemData8-15
8-bit bus:
not applicable
Writes only. Indicates valid write data on MemData8-15.
Reads and writes. Behaves as address bit 0 with same
timing as MemAddr1-19.
Table 9.2 Strobe allocation
9.3 External accesses
The EMI differentiates accesses and transactions. An access is the lowest denominator of a
transaction. Since the ST20 word size is 32 bits, several accesses are required to complete a
transaction in most cases. The following are cases where several accesses may not be required:
• CPU executes a sb (store byte), lb (load byte) or ss (store sixteen), ls (load sixteen) instruc-
tion.
• CPU is executing a move2dnonzero (2D block copy non-zero bytes) or move2dzero (2D
block copy zero bytes) instruction and the data dictates that certain bytes are not to be
written.
• The first or last DMA operation to or from a link is to a non word aligned byte address.
Figure 9.2 shows the generic EMI activity during a read access and the configurable parameters.
The rising edge of notMemOE always occurs at the end of the read access just after the data is
latched on chip. notMemWB0 is always inactive during a read access. notMemWB1 activity
during a read access depends on the bus width for the bank. The strobe is inactive if the bus width
is configured to be 16-bit. If the bus width is configured to be 8-bit, notMemWB1behaves as
address bit 0 with the same timing as MemAddr1-19.
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