ST20-GP1
Bus
width
Valid
bytes
<3:0>
Number of
accesses
required
MemAddr1
1234
notMemWB1
1234
notMemWB0
1234
8
0001
8
0010
8
0011
8
0100
8
0101
8
0110
8
0111
8
1000
8
1001
8
1010
8
1011
8
1100
8
1101
8
1110
8
1111
16
0001
16
0010
16
0011
16
0100
16
0101
16
0110
16
0111
16
1000
16
1001
16
1010
16
1011
16
1100
16
1101
16
1110
16
1111
1
L - - - L - - - A- - -
1
L - - - H- - - A- - -
2
L L - - L H- - AA- -
1
H- - - L - - - A- - -
2
L H- - L L - - AA- -
2
L H- - HL - - AA- -
3
L L H- L HL - AAA-
1
H- - - H- - - A- - -
2
L H- - L H- - AA- -
2
L H- - HH- - AA- -
3
L L H- L HH- AAA-
2
HH- - L H- - AA- -
3
L HH- L L H- AAA-
3
L HH- HL H- AAA-
4
L L HHL HL HAAAA
1
L - - - I - - - A- - -
1
L - - - A- - - I - - -
1
L - - - A- - - A- - -
1
H- - - I - - - A- - -
2
L H- - I I - - AA- -
2
L H- - AI - - I A- -
2
L H- - AI - - AA- -
1
H- - - A- - - I - - -
2
L H- - I A- - AI - -
2
L H- - AA- - I I - -
2
L H- - AA- - AI - -
1
H- - - A- - - A- - -
2
L H- - I A- - AA- -
2
L H- - AA- - I A- -
2
L H- - AA- - AA- -
Table 9.3 Transaction composition for valid bytes on internal memory bus
Key: L = low for whole access
H = high for whole access
A = active on write accesses
I = inactive for whole access
The EMI buffers subsequent transactions which may occur, without intervening dead cycles except
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