ST20-GP1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST20-GP1 Datasheet PDF : 116 Pages
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ST20-GP1
status of the lock and stall bits. Table 9.6 shows the format of the EMIConfigStatus register.
EMIConfigStatus
EMI base address + #20
Read only
Bit Bit field
0 WrittenBank0
1 WrittenBank1
2 WrittenBank2
3 WrittenBank3
4 WriteLock
5 MemStall
31:6
Function
Bank 0 configuration has been written to using a devsw instruction.
Bank 1 configuration has been written to using a devsw instruction.
Bank 2 configuration has been written to using a devsw instruction.
Bank 3 configuration has been written to using a devsw instruction.
EMIConfigData0-3 registers are write protected.
EMIConfigStall has been set.
Reserved
Table 9.6 EMIConfigStatus register format
EMIConfigStall register
The EMIConfigStall register can be used to stall the EMI. When set it prevents the EMI from
accepting further requests from the CPU or communications subsystems. Its main use is intended
to be in systems which anticipate turning the power off; the EMI must be inactive during such an
event, otherwise battery backed memory may be corrupted.
This register, once set, can only be cleared by resetting the ST20-GP1.
EMIConfigStall
Bit
Bit field
0
EMIStall
EMI base address + #30
Write only
Function
When set, this bit prevents the arbiter from granting any more accesses to the
memory subsystem.
Table 9.7 EMIConfigStall register format
9.6 Reset and bootstrap behavior
Table 9.8 shows the state of the EMI signals during reset. MemAddr2-19 are driven with a copy of
the value on the internal memory bus2-19.
Pins
Value
MemAddr2-19
MemAddr1
notMemCE0-3
notMemOE0-1
notMemWB0-1
MemData0-15
Valid
High
All high
All high
All high
High impedance
Table 9.8 EMI signal values during reset
Table 9.9 shows the configuration values for all banks during and after reset. If the BootSource0-1
pins indicate that the ST20-GP1 will boot from ROM, the BusWidth is set to the correct value as
the ST20-GP1 comes out of reset.
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