ST20-GP1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST20-GP1

GPS PROCESSOR

STMicroelectronics 

ST20-GP1

SysRatio

The SysRatio register is a read only register and gives the speed at which the system PLL is running.

It contains the relevant PLL multiply ratio when using the PLL, or contains the value ‘1’ when in

TimesOneMode for the PLL.

SysRatio

Bit

Bit field

5:0

SysRatio

LPC base address + #500

Function

PLL speed, as follows:

SysRatio PLL

1 x1 TimesOneMode

2 x1 16.368 MHz

4 x2 32.736 MHz

6 x3 RESERVED

Read

Table 10.9 SysRatio register format

WdEnable

Setting the WdEnable register enables the low power alarm counter to be used as a watchdog

timer.

WdEnable

Bit

Bit field

0

WdEnable

LPC base address + #510

Read/Write

Function

Determines whether the low power alarm is set to operate as an alarm or as a

watchdog timer.

0 alarm

1 watchdog

Table 10.10 WdEnable register format

WdFlag

This register can be used to determine if the device was reset by the notRST input or by a

watchdog time-out.

Note that this bit is not reset by the CPUReset input.

WdFlag

Bit

Bit field

0

WdFlag

LPC base address + #514

Read

Function

Watchdog timer flag.

0 set to 0 by an external notRST

1 set to 1 when the watchdog counter is #1 and the WdEnable register is 1

Table 10.11 WdFlag register format

10.4 Clocking sources

The low power timer and alarm must be clocked at all times by one of the following clocking sources:

• External clock input (LPClockIn) — this clock must not be more than one eighth of the sys-

tem clock rate. In this case the LPClockOsc pin should not be connected on the board.

• Watch crystal, as in Figure 10.1.

65/116

®

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