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STA120D View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
STA120D
ST-Microelectronics
STMicroelectronics 
STA120D Datasheet PDF : 15 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
STA120
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VD+, VA+ Power Supply Voltage
VIN
Input Voltage ( excluding pins 9, 10)
Tamb Ambient Operating Temperature (power applied)
Tstg
Storage Temperature
Value
Unit
4
V
-0.3 to VD+ +0.3
V
-30 to +85
°C
-40 to 150
°C
PIN CONNECTIONS (Top view)
C
Cd/F1
Cc/F0
Cb/E2
Ca/E1
C0/E0
VD+
DGND
RXP
RXN
FSYNC
SCK
CS12/FCK
U
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
D97AU609A
VERF
Ce/F2
SDATA
ERF
M1
M0
VA+
AGND
FILT
MCK
M2
M3
SEL
CBL
PINS DESCRIPTION
N.
Name
Description
Power Supply
7
VD+ Positive Digital Power.Positive supply for the digital section. Nominally 3.3V.
8
DGND Digital Ground.Ground for the digital section.
21
AGND Analog Ground.Ground for the analog section. AGND should be connected to same ground as
DGND.
22
VA+ Positive Analog Power.Positive supply for the analog section. Nominally 3.3V.
Audio Output Interface
11
12
17, 18,
23, 24
26
FSYNC
SCK
M2, M3,
M1, M0
SDATA
Frame Sync.Delineates the serial data and may indicate the particular channel, left or right and
may be an input or output. The format is based on M0, M1, M2 and M3 pins.
Serial Clock.Serial clock for SDATA pin which can be configured (via the M0, M1, M2 and M3
pins) as an input or output and can sample data on the rising or falling edge. As an output, SCK
will generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample
must be provided in all normal modes.
Serial Port Mode Selects.Selects the format of Fsync and the sample edge of SCK with respect
to SDATA.
Serial Data. Audio data serial output pin.
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