STA120D View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA120D Datasheet PDF : 15 Pages
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STA120
This timing is illustrated in Figure 5.
The C output contains the channel status bits with CBL rising indicating the start of a new channel status
block. CBL is high for the first four bytes of channel status (32 frames or 64 samples) and low for the last
20 bytes of channel status (160 frames or 320 samples).
The U output contains the User Channel data. The V bit is OR'ed with the ERF flag and output on the
VERF pin. This indicates that the audio sample may be in error and can be used by interpolation filters to
interpolate through the error.
ERF being high indicates a serious error occurred on the transmission line. There are three errors that
cause ERF to go high: a parity error or biphase coding violation during that sample, or an out of lock PLL
receiver. Timing for the above pins is illustrated in Figure 5.
Multifunction Pins
There are seven multifunction pins which contain either error and received frequency information, or chan-
nel status information, selectable by SEL.
Figure 3. Audio Serial Port Formats
FORMAT 0:
M2
0
M1
0
M0
0
FSYNC(out)
LEFT
SCK(out)
RIGHT
SDATA(out)
MSB
FORMAT 1:
FSYNC(in)
001
SCK(in)
LSB
LEFT
MSB
LSB
RIGHT
MSB
SDATA(out)
FORMAT 2:
01
FSYNC(out)
0
SCK(out)
MSB
LEFT
LSB
MSB
RIGHT
LSB
MSB
SDATA(out)
MSB
LSB
MSB
LSB
MSB
FORMAT 3:
FSYNC(in)
LEFT
011
SCK(in)
RIGHT
SDATA(out)
MSB
LSB
MSB
LSB
MSB
FORMAT 4:
FSYNC(out)
LEFT
100
SCK(out)
RIGHT
SDATA(out)
MSB
FORMAT 5:
10
FSYNC(out)
1
SCK(out)
LSB
LEFT
MSB
LSB
RIGHT
MSB
SDATA(out) LSB
MSB
LSB
MSB
LSB
FORMAT 6:
11
FSYNC(out)
0
SCK(out)
16 Bits
LEFT
16 Bits
RIGHT
SDATA(out) LSB
MSB
LSB
MSB
LSB
FORMAT 7:
11
FSYNC(out)
1
SCK(out)
18 Bits
LEFT
18 Bits
RIGHT
SDATA(out) MSB
LSB
MSB
LSB
MSB
D97AU610
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