STA120D View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA120D Datasheet PDF : 15 Pages
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STA120
Figure 1. Circuit Diagram
3.3V
ANALOG
3.3V
DIGITAL
RECEIVER
CIRCUIT
(See Appendix A)
0.1µF
AGND
RXP
RXN
CS12/FCK
CHANNEL STATUS
and/or
ERROR/FREQUENCY
REPORTING
SEL
ERF
C/E-F bits
FILT
330Ω
0.47µF
15nF
0.1µF
VA+
VD+
22
21
7
MCK
19
9
VERF
28
SCK
10
12
SDATA
26
13
STA120
FSYNC
11
16
25
C
1
6
U
14
CBL
20
15
8
DGND
AUDIO
DATA
PROCESSOR
µCONTROLLER
or
LOGIC
D97AU611
GENERAL DESCRIPTION
The STA120 is a monolithic CMOS circuit that receives and decodes audio and digital data according to
the AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340/1201 interface standards.
It contains a RS422 line receiver and Phase-Locked Loops (PLL) that recovers the clock and synchroni-
zation signals and de-multiplexes the audio and digital data. The STA120 de-multiplexes the channel sta-
tus, user and validity information directly to serial output pins with dedicated pins for the most important
channel status bits.
Line Receiver
The line receiver can decode differential as well as single ended inputs. The receiver consits of a differ-
ential input Schmitt trigger with 50mV of hysteresis. The hysteresis prevents noisy signals from corrupting
the phase detector. Appendix A contains more information on how to configure the line receivers for dif-
ferential and single ended signals.
Clocks and Jitter Attenuation
The primary function of this chip is to recover audio data and low jitter clocks from a digital audio trans-
mission line. The clocks that can be generated are MCK (256xFS), SCK (64xFS), and FSYNC (FS or
2xFS). MCK is the output of the voltage controlled oscillator which is a component of the PLL. The PLL
consists of phase and frequency detectors, a second-order loop filter, and a voltage controlled oscillator.
All components of the PLL are on chip with the exception of a resistor and capacitors used in the loop filter.
This filter is connected between the FILT pin and AGND. The closed-loop transfer function, which speci-
fies the PLL's jitter attenuation characteristics, is shown in Figure 2.
The loop will begin to attenuate jitter at approximately 25kHz with another pole at 80kHz and will have
50dB of attenuation by 1MHz. Since most data jitter introduced by the transmission line is high in frequen-
cy, it will be strongly attenuated.
Multiple frequency detectors are used to minimize the time it takes the PLL to lock to the incoming data
stream and to prevent false lock conditions. When the PLL is not locked to the incoming data stream, the
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