STULPI01ATBR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STULPI01ATBR Datasheet PDF : 44 Pages
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Block description
STULPI01A - STULPI01B
6.14
Car kit (UART) mode
This mode is entered by writing to the car kit mode bit in the interface control register.
STULPI01 does not implement all features of car kit mode, only the UART functionality is
preserved.
Table 10. Car kit signals mapping
Default car kit signals mapping (UART_DIR = 0)
Signal
ULPI lines
TXD
RXD
DATA[0] (input) ->
DATA[1] (output) <-
reserved
DATA[2] (input)
INT
DATA[3] (output)
Car kit signals mapping (UART_DIR = 1)
Signal
ULPI lines
TXD
DATA[0] (input) ->
RXD
DATA[1] (output) <-
reserved
INT
DATA[2] (input)
DATA[3] (output)
USB lines
DM (output)
DP (input)
USB lines
DP (output)
DM (input)
TXD or RXD paths are activated only when corresponding bits TXD_EN/RXD_EN in car kit
Control Register bits (Table 23) are set.
UART_2V7 bit controls the voltage level of UART signaling. In case 2V7 volt signaling is
used, after the UART mode is entered, PLL is disabled and the voltage on the regulator
output starts to decrease to 2.7 V. After time marked as tUARTON2V7 the TXD output on USB
bus is enabled.
When leaving car kit mode, TXD is disabled immediately when STP pin is asserted. The
time required to exit car kit mode is equivalent to the time needed for PLL startup.
Note:
When 3.3 volt UART signaling is selected, TXD line is enabled immediately after entering
car kit mode, and disabled after exit from this mode.
When car kit mode is used with 2V7 signaling, PLL and output clock is always stopped
regardless on the setting of ClockSuspendM bit.
6.15
22/44
Low power mode
STULPI01 enters low power mode when SuspendM bit in interface control register is set to
0b. Most of the references are turned off, PLL and clock are turned off, but the full wake-up
capability as defined in the ULPI specification is still maintained.
When in low power mode, the PHY drives D3-D0 with the signals listed in table below. Line
state is driven combinatorially from the SE receivers. The INT signal is asserted whenever
any unmasked interrupt occurs. The PHY latches interrupt events directly from analog
circuitry because the clock is powered down.
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