STULPI01ATBR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STULPI01ATBR

High speed USB On-The-Go ULPI transceiver

STMicroelectronics 

Block description

STULPI01A - STULPI01B

6.18.3

6.18.4

Note:

6.18.5

6.18.6

Note:

External clock detection

The square wave clock can be applied to the oscillator input. The input square wave clock

amplitude is referenced to the 1V8VIO voltage.

The XO pin can be left floating or grounded.

Reset behavior

Typical startup sequence is shown in Figure 9.

STULPI01 contains internal power-on-reset generator which senses the V3V3V and V1V2V

voltage. Assertion of RESETn is not necessary for proper initialization. However, if required,

this pin can be also used. The internal reset signal is the combination of the signal from

RESETn pin and the signal from the internal power-on-reset circuit.

When RESETn is asserted, all internal registers are reset to their default values, the output

DIR signal is driven to '1', and data lines pulled low by weak pull-downs.

During reset the STP pin can be driven low, high, or can be left floating. It will be pulled up

by internal pull-up and the ULPI interface enters a holding state.

During the reset state the NXT signal is driven low and the CLK is driven high.

When the PLL is stabilized, the clock on the CLK pin is enabled, and DIR is deasserted.

NOTE: The minimum duration of the external reset signal is TRESETEXT. (See chapter

Crystal or external clock detection).

When internal POR reset is asserted, the reset procedure is equivalent to the RESETn

signal, with the only exception being that the ULPI lines are in high impedance state. All pull-

downs and pull-ups on the ULPI signals are also disabled.

Interface protection

The STULPI01 activates weak pull-downs on data lines and pull-up on the STP during reset

and holding state. These are to provide interface protection during startup and anytime the

link is not able to drive the ULPI lines properly.

The holding state is entered when the controller drives the STP for more than 1 clock cycle.

Any command on the ULPI bus is ignored in this state. For more information, see ULPI

specification 1.1, section 3.12 (Safeguarding PHY input signals).

Interface protection can be switched off at any time after startup in order to save power, by

writing the Interface Protect Disable bit in the Interface Control register to 1b.

Software reset

The STULPI01 supports software reset by writing the RESET bit in the function control

register to 1b.

During the software reset, DIR is asserted and the pull down resistors on data lines are

enabled, but the ULPI registers remain unaffected. Software reset initializes UTMI core logic

only. Also, during software reset, external clock detection, SDR mode selection is not

performed, and clock is not turned off (PLL is not re-started).

NOTE: Software reset is not required in the startup procedure for the STULPI. The chip is

ready for operation after the hardware reset procedure.

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