PIC16LF1826-I/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LF1826-I/SS

18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC16F/LF1826/27

8.5.9

PIR4 REGISTER(1)

The PIR4 register contains the interrupt flag bits, as

shown in Register 8-9.

Note 1: The PIR4 register is available only on the

PIC16F/LF1827 device.

2: Interrupt flag bits are set when an inter-

rupt condition occurs, regardless of the

state of its corresponding enable bit or the

Global Enable bit, GIE, of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

REGISTER 8-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4(1)

U-0

—

bit 7

U-0

U-0

U-0

U-0

U-0

R/W/HS-0/0 R/W/HS-0/0

—

—

—

—

—

BCL2IF

SSP2IF

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS = Bit is set by hardware

bit 7-2

bit 1

bit 0

Unimplemented: Read as ‘0’

BCL2IF: MSSP2 Bus Collision Interrupt Flag bit

1 = A Bus Collision was detected (must be cleared in software)

0 = No Bus collision was detected

SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit

1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)

0 = Waiting to Transmit/Receive/Bus Condition in progress

Note 1: This register is only available on PIC16F/LF1827.

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE TMR0IF

INTF

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA

PS2

PS1

PIE1

TMR1GIE ADIE

RCIE

TXIE

SSP1IE CCP1IE TMR2IE

PIE2

PIE3(1)

PIE4(1)

OSFIE

C2IE

C1IE

EEIE

BCL1IE

—

—

—

—

CCP4IE CCP3IE TMR6IE

—

TMR4IE

—

—

—

—

—

—

BCL2IE

PIR1

TMR1GIF ADIF

RCIF

TXIF

SSP1IF CCP1IF TMR2IF

PIR2

PIR3(1)

PIR4(1)

OSFIF

C2IF

C1IF

EEIF

BCL1IF

—

—

—

—

CCP4IF CCP3IF TMR6IF

—

TMR4IF

—

—

—

—

—

—

BCL2IF

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.

Note 1: PIC16F/LF1827 only.

Bit 0

IOCIF

PS0

TMR1IE

CCP2IE(1)

—

SSP2IE

TMR1IF

CCP2IF(1)

—

SSP2IF

Register

on Page

91

177

92

93

94

95

96

97

98

99

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 99

Share Link: