OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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ORCA Series 2 FPGAs
Data Sheet
November 2006
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
Pin
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad 2C/2T15A/B Pad
Function
W10
V10
Y10
S Y11
W11
V11
E U11
Y12
W12
IC V12
D U12
Y13
V W13
E V13
Y14
E U W14
Y15
V14
D IN W15
Y16
U14
T V15
T W16
Y17
C V16
N W17
Y18
E U16
O V17
L W18
Y19
E C V18
W19
S IS Y20
W20
V19
D U19
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
—
—
PB11A
—
—
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
—
DONE
RESET
PRGM
PR12A
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
—
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14B
PB14C
PB14D
DONE
RESET
PRGM
PR14A
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14B
PB15A
PB15B
PB15C
PB15D
PB16A
PB16B
PB16C
PB16D
DONE
RESET
PRGM
PR16A
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14D
PB15A
PB15D
PB16A
PB16D
PB17A
PB17C
PB17D
PB18A
PB18B
PB18C
PB18D
DONE
RESET
PRGM
PR18A
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14B
PB14C
PB14D
PB15A
PB15D
PB16A
PB16D
PB17A
PB17D
PB18A
PB18D
PB19A
PB19D
PB20A
PB20B
PB20D
DONE
RESET
PRGM
PR20A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-HDC
I/O
I/O
I/O
I/O-LDC
I/O
I/O
I/O
I/O
I/O
I/O-INIT
I/O
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DONE
RESET
PRGM
I/O-M0
U18
—
PR14C
PR16C
PR18C
PR20D
I/O
T17
—
PR14D
PR16D
PR18D
PR19A
I/O
V20
—
PR13A
PR15A
PR17A
PR19D
I/O
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
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