OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
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Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
Pin
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad 2C/2T15A/B Pad
Function
P3
PL10D
R2
PL10C
T1
PL10B
S P4
PL10A
R3
PL11D
T2
PL11C
E U1
PL11B
T3
PL11A
U2
—
IC V1
PL12D
D T4
PL12C
U3
PL12B
V V2
—
E W1
—
V3
—
E U W2
PL12A
Y1
CCLK
Y2
PB1A
D IN W4
—
V4
PB1B
U5
PB1C
T Y3
PB1D
T Y4
—
V5
—
C W5
PB2A
N Y5
PB2B
V6
PB2C
E U7
PB2D
O W6
PB3A
L Y6
PB3B
V7
PB3C
E C W7
PB3D
Y7
PB4A
S IS V8
PB4B
W8
PB4C
Y8
PB4D
D U9
PB5A
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
PL13A
PL14D
PL14C
PL14B
PL14A
CCLK
PB1A
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PL12D
PL12C
PL12B
PL13D
PL13B
PL13A
PL14D
PL14C
PL15D
PL15C
PL15B
PL15A
PL16D
PL16C
PL16B
PL16A
CCLK
PB1A
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3B
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PL13D
PL13B
PL14D
PL14B
PL14A
PL15D
PL15B
PL16D
PL17D
PL17C
PL17B
PL17A
PL18D
PL18C
PL18B
PL18A
CCLK
PB1A
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PB3D
PB4D
PB5A
PB5B
PB5D
PB6A
PB6B
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PL14D
PL14B
PL15D
PL15B
PL15A
PL16D
PL16B
PL17D
PL18D
PL18C
PL18A
PL19D
PL19C
PL19A
PL20D
PL20A
CCLK
PB1A
PB1D
PB2A
PB2D
PB3A
PB3C
PB3D
PB4D
PB5D
PB6A
PB6B
PB6D
PB7A
PB7B
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
I/O-A12
I/O
I/O
I/O-A13
I/O
I/O
I/O
I/O-A14
I/O-VDD5
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A15
CCLK
I/O-A16
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-A17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V9
PB5B
PB6B
PB7B
PB8B
PB9B
I/O
W9
PB5C
PB6C
PB7C
PB8C
PB9C
I/O
Y9
PB5D
PB6D
PB7D
PB8D
PB9D
I/O
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
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