OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
Pin
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad 2C/2T15A/B Pad
Function
U20
PR12B
T18
PR12C
T19
PR12D
S T20
PR11A
R18
PR11B
P17
PR11C
E R19
PR11D
R20
PR10A
P18
PR10B
IC P19
PR10C
D P20
PR10D
N18
PR9A
V N19
PR9B
E N20
PR9C
M17
PR9D
E U M18
PR8A
M19
PR8B
M20
PR8C
D IN L19
PR8D
L18
PR7A
L20
PR7B
T K20
PR7C
T K19
PR7D
K18
PR6A
C K17
PR6B
N J20
PR6C
J19
PR6D
E J18
PR5A
O J17
PR5B
L H20
PR5C
H19
PR5D
E C H18
PR4A
G20
PR4B
S IS G19
PR4C
F20
PR4D
G18
PR3A
D F19
PR3B
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR15B
PR15C
PR15D
PR14A
PR14C
PR14D
PR13A
PR13B
PR13C
PR12A
PR12B
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR4B
PR17B
PR17C
PR17D
PR16A
PR16D
PR15A
PR15C
PR15D
PR14A
PR14D
PR13A
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR18A
PR18B
PR18D
PR17A
PR17D
PR16A
PR16C
PR16D
PR15A
PR15D
PR14A
PR13A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-M1
I/O
I/O-VDD5
I/O
I/O-M2
I/O
I/O
I/O
I/O-M3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-VDD5
I/O
I/O
I/O
I/O-CS1
I/O
I/O
I/O
I/O-CS0
I/O
E20
PR3C
PR4C
PR4C
PR5B
PR6B
I/O
G17
PR3D
PR4D
PR4D
PR5D
PR6D
I/O
F18
PR2A
PR3A
PR3A
PR4A
PR5A
I/O-RD
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
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