ORCA Series 2 FPGAs
Data Sheet
November 2006
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
Pin
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad 2C/2T15A/B Pad
Function
U8
VSS
U13
VSS
U17
VSS
S B1
VDD
D6
VDD
D11
VDD
E D15
VDD
F4
VDD
F17
VDD
IC K4
VDD
D L17
VDD
R4
VDD
V R17
VDD
E U6
VDD
U10
VDD
E U U15
VDD
W3
—
J10
VSS
D IN J11
VSS
J12
VSS
J9
VSS
T K10
VSS
T K11
VSS
K12
VSS
C K9
VSS
N L10
VSS
L11
VSS
E L12
VSS
O L9
VSS
L M10
VSS
M11
VSS
E C M12
VSS
M9
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
No Connect
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
S IS Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
D The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
100
Lattice Semiconductor