OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C06A, OR2T08A, OR2C/2T10A, OR2C12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
Pin
2C06A Pad
2T08A Pad
2C/2T10A Pad
2C12A Pad 2C/2T15A/B Pad
Function
B10
PT6D
PT7D
PT8D
PT9D
PT10D
I/O
C10
PT6C
PT7C
PT8C
PT9C
PT10C
I/O
D10
PT6B
PT7B
PT8B
PT9B
PT10B
I/O-VDD5
S A9
PT6A
PT7A
PT8A
PT9A
PT10A
I/O-D2
B9
PT5D
PT6D
PT7D
PT8D
PT9D
I/O-D1
C9
PT5C
PT6C
PT7C
PT8C
PT9C
I/O
E D9
PT5B
PT6B
PT7B
PT8B
PT9B
I/O
A8
PT5A
PT6A
PT7A
PT8A
PT9A
I/O-D0/DIN
B8
PT4D
PT5D
PT6D
PT7D
PT8D
I/O
IC C8
PT4C
PT5C
PT6C
PT7C
PT8C
I/O
D A7
PT4B
PT5B
PT6B
PT7B
PT8B
I/O
B7
PT4A
PT5A
PT6A
PT7A
PT8A
I/O-DOUT
V A6
PT3D
PT4D
PT5D
PT6D
PT7D
I/O
E C7
PT3C
PT4C
PT5A
PT6A
PT7A
I/O
B6
PT3B
PT4B
PT4D
PT5C
PT6C
I/O
E U A5
PT3A
PT4A
PT4A
PT5A
PT6A
I/O-TDI
D7
PT2D
PT3D
PT3D
PT4D
PT5D
I/O
C6
PT2C
PT3C
PT3C
PT4A
PT5A
I/O-VDD5
D IN B5
PT2B
PT3B
PT3B
PT3D
PT4D
I/O
A4
PT2A
PT3A
PT3A
PT3A
PT4A
I/O-TMS
C5
—
PT2D
PT2D
PT2D
PT3D
I/O
T B4
PT1D
PT2C
PT2C
PT2C
PT3A
I/O
T A3
PT1C
PT2B
PT2B
PT2B
PT2D
I/O
D5
PT1B
PT2A
PT2A
PT2A
PT2A
I/O
C C4
—
PT1D
PT1D
PT1D
PT1D
I/O
N B3
—
PT1C
PT1C
PT1C
PT1C
I/O
B2
—
PT1B
PT1B
PT1B
PT1B
I/O
E A2
PT1A
PT1A
PT1A
PT1A
PT1A
I/O-TCK
O C3 RD_DATA/TDO RD_DATA/TDO RD_DATA/TDO RD_DATA/TDO RD_DATA/TDO RD_DATA/TDO
L A1
VSS
VSS
VSS
VSS
VSS
VSS
D4
VSS
VSS
VSS
VSS
VSS
VSS
E C D8
VSS
VSS
VSS
VSS
VSS
VSS
D13
VSS
VSS
VSS
VSS
VSS
VSS
S IS D17
VSS
VSS
VSS
VSS
VSS
VSS
H4
VSS
VSS
VSS
VSS
VSS
VSS
H17
VSS
VSS
VSS
VSS
VSS
VSS
D N4
VSS
VSS
VSS
VSS
VSS
VSS
N17
VSS
VSS
VSS
VSS
VSS
VSS
U4
VSS
VSS
VSS
VSS
VSS
VSS
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lattice Semiconductor
99
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