OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
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Description
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OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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ORCA Series 2 FPGAs
Data Sheet
November 2006
Special Function Blocks (continued)
s
Boundary Scan
The increasing complexity of integrated circuits (ICs)
TMS TDI
TCK
TDO
U2
net a
net b
net c
TMS TDI
TCK
TDO
U1
and IC packages has increased the difficulty of testing
printed-circuit boards (PCBs). To address this testing
problem, the IEEE standard 1149.1 - 1990 (IEEE Stan-
dard Test Access Port and Boundary-Scan Architec-
S ture) is implemented in the ORCA series of FPGAs. It
allows users to efficiently test the interconnection
between integrated circuits on a PCB as well as test
E the integrated circuit itself. The IEEE 1149.1 standard
is a well-defined protocol that ensures interoperability
among boundary-scan (BSCAN) equipped devices
IC from different vendors.
D The IEEE 1149.1 standard defines a test access port
(TAP) that consists of a 4-pin interface with an optional
reset pin for boundary-scan testing of integrated cir-
V E cuits in a system. The ORCA series FPGA provides
four interface pins: test data in (TDI), test mode select
E (TMS), test clock (TCK), and test data out (TDO). The
U PRGM pin used to reconfigure the device also resets
the boundary-scan logic.
D The user test host serially loads test commands and
IN test data into the FPGA through these pins to drive out-
puts and examine inputs. In the configuration shown in
Figure 47, where boundary scan is used to test ICs,
T T test data is transmitted serially into TDI of the first
BSCAN device (U1), through TDO/TDI connections
between BSCAN devices (U2 and U3), and out TDO of
C N the last BSCAN device (U4). In this configuration, the
TMS and TCK signals are routed to all boundary-scan
ICs in parallel so that all boundary-scan components
E operate in the same state. In other configurations, mul-
O tiple scan paths are used instead of a single ring. When
L multiple scan paths are used, each ring is indepen-
dently controlled by its own TMS and TCK signals.
E C Figure 48 provides a system interface for components
used in the boundary-scan testing of PCBs. The three
S IS major components shown are the test host, boundary-
scan support circuit, and the devices under test
(DUTs). The DUTs shown here are ORCA Series
FPGAs with dedicated boundary-scan circuitry. The
D test host is normally one of the following: automatic test
TMS TDI
TCK
TDO
U3
TMS TDI
TCK
TDO
U4
TDI
TMS
TCK
TDO
SEE ENLARGED VIEW BELOW
TDO TCK TMS TDI
PT[ij]
TAPC
BYPASS
REGISTER
SCAN
IN
BSC
BDC DCC
SCAN
OUT
INSTRUCTION
REGISTER
SCAN
OUT
P_IN
P_TS
P_OUT
SCAN
IN
PL[ij]
BSC
DCC
BDC
P_TS
P_OUT
P_IN
PLC
ARRAY
P_IN
P_OUT
P_TS
BSC
BDC
DCC
PR[ij]
SCAN
IN
P_OUT
P_TS
P_IN
SCAN
OUT
SCAN
OUT
BSC
DCC BDC
SCAN
IN
PB[ij]
ENLARGED VIEW
Key:
Fig.34.a(F).1C
BSC = boundary-scan cell, BDC = bidirectional data cell,
and DCC = data control cell.
Figure 47. Printed-Circuit Board with Boundary-
Scan Circuitry
The boundary-scan support circuit shown in Figure 48
is the 497AA Boundary-Scan Master (BSM). The BSM
off-loads tasks from the test host to increase test
equipment (ATE), a workstation, a PC, or a micropro-
throughput. To interface between the test host and the
cessor.
DUTs, the BSM has a general microprocessor interface
and provides parallel-to-serial/serial-to-parallel conver-
sion, as well as three 8K data buffers.
56
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