AD9269(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9269 Datasheet PDF : 40 Pages
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AD9269
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNRLF) at a given input frequency (fINPUT) due to
jitter (tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 (−SNRLF /10) ]
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 55.
80
75
0.05ps
70
0.2ps
65
60
0.5ps
55
1.0ps
50
1.5ps
2.0ps
45
3.0ps 2.5ps
1
10
100
1k
FREQUENCY (MHz)
Figure 55. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9269.
To avoid modulating the clock signal with digital noise, keep power
supplies for clock drivers separate from the ADC output driver
supplies. Low jitter, crystal-controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), it should be retimed by
the original clock at the last step.
For more information, see the AN-501 Application Note and the
AN-756 Application Note, available on www.analog.com.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 56, the analog core power dissipated by the
AD9269 is proportional to its sample rate. The digital power dis-
sipation of the CMOS outputs is determined primarily by the
strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (34, in the case of the
AD9269).
210
190
AD9269-80
170
150
AD9269-65
130
110
AD9269-40
90
AD9269-20
70
10
20
30
40
50
60
70
80
CLOCK RATE (MSPS)
Figure 56. Analog Core Power vs. Clock Rate
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is estab-
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 56 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
Rev. 0 | Page 24 of 40
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