CHANNEL/CHIP SYNCHRONIZATION
The AD9269 has a SYNC input that offers the user flexible
synchronization options for synchronizing sample clocks
across multiple ADCs. The input clock divider can be enabled
to synchronize on a single occurrence of the SYNC signal or on
every occurrence. The SYNC input is internally synchronized to
AD9269
the sample clock; however, to ensure that there is no timing
uncertainty between multiple parts, the SYNC input signal should
be externally synchronized to the input clock signal, meeting the
setup and hold times that are shown in Table 5. Drive the SYNC
input using a single-ended CMOS-type signal.
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