AD9269(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9269 Datasheet PDF : 40 Pages
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AD9269
Addr.
(Hex)
0x0D
0x0E
0x10
0x14
0x15
0x16
0x17
0x19
0x1A
0x1B
0x1C
0x24
Register
Name
Test mode (local)
BIST enable
Offset adjust
(local)
Output mode
OUTPUT_ADJUST
OUTPUT_PHASE
OUTPUT_DELAY
USER_PATT1_LSB
USER_PATT1_MSB
USER_PATT2_LSB
USER_PATT2_MSB
MISR_LSB
(MSB)
Bit 7
Bit 6
User test mode
(local)
00 = single
01 = alternate
10 = single once
11 = alternate
once
Bit 5
Reset PN
long gen
Open
Open Open
Bit 4
Reset PN
short
gen
Open
Bit 3 Bit 2
Bit 1
(LSB)
Bit 0
Output test mode [3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one/zero word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
Open BIST init Open
BIST
enable
8-bit device offset adjustment [7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
00 = 3.3 V CMOS
10 = 1.8 V CMOS
Output mux
enable
(interleaved)
Output
disable
(OEB)
(local)
Open
Output
invert
(local)
00 = offset binary
01 = twos
complement
10 = gray code
11 = offset binary
(local)
3.3 V DCO
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
1.8 V DCO drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
3.3 V data
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
1.8 V data
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
DCO
output
polarity
0=
normal
1=
inverted
(local)
Open
Open
Open
Open
Input clock phase adjust, Bits[2:0]
(Value is number of input clock
cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Enable
DCO
delay
Open Enable
data
delay
Open
Open
DCO/data delay, Bits[2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
B7
B6
B5
B4
B3
B2
B1
B0
B15
B14 B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B15
B14 B13
B12
B11
B10
B9
B8
Open
Open Open
Open
Open Open
Open B0
Default
Value
(Hex)
0x00
Comments
When set, the test
data is placed on
the output pins
in place of
normal data
0x00
0x00
0x00
When Bit 0 is set,
the BIST function
is initiated
Device offset trim
Configures the
outputs and the
format of the data
0x22
Determines
CMOS output
drive strength
properties
0x00
0x00
On devices that
utilize global
clock divide,
determines
which phase of
the divider
output is used to
supply the
output clock;
internal latching
is unaffected
This sets the fine
output delay of
the output clock
but does not
change internal
timing
0x00
0x00
0x00
0x00
0x00
User-Defined
Pattern 1, LSB
User-defined
Pattern 1, MSB
User-Defined
Pattern 2, LSB
User-Defined
Pattern 2, MSB
Least significant
byte of MISR;
read only
Rev. 0 | Page 33 of 40
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