AD9269(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9269
(Rev.:Rev0)

16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter

Analog Devices

AD9269 Datasheet PDF : 40 Pages

First Prev 31 32 33 34 35 36 37 38 39 40

AD9269

Addr.

(Hex)

0x2A

Name

Features

(MSB)

Bit 7

Open

Bit 6 Bit 5

Open Open

Bit 4

Open

Bit 3

Open

Bit 2

Open

Bit 1

Open

(LSB)

Bit 0

OR OE

(local)

0x2E Output assign

Open

Open Open

Open

Open Open

Open

Digital feature control

0x100 Sync control

(global)

0x101 USR2

0x110 QEC Control 0

0x111 QEC Control 1

0x112

0x113

0x114

0x116

0x117

0x118

0x119

0x11A

0x11B

0x11C

0x11D

QEC gain

bandwidth control

QEC phase

bandwidth control

QEC DC

bandwidth control

QEC Initial Gain 0

QEC Initial Gain 1

QEC Initial Phase 0

QEC Initial Phase 1

QEC Initial DC I 0

QEC Initial DC I 1

QEC Initial DC Q 0

QEC Initial DC Q 1

Open

Open Open

Enable

OEB

(Pin 47)

(local)

Open

Open Freeze DC

Open

Enable

GCLK

detect

Clock

divider

sync

only

Run

GCLK

Clock

divider

sync

enable

Open

Freeze

phase

Open

Freeze

gain

Open

enable

Phase

enable

Force

phase

KEXP_GAIN

KEXP_PHASE

KEXP_DC

Initial gain, Bits[7:0]

Initial gain, Bits[14:8]

Initial phase, Bits[7:0]

Initial phase, Bits[12:8]

Initial DC I, Bits[7:0]

Initial DC I, Bits[13:8]

Initial DC Q, Bits[7:0]

Initial DC Q, Bits[13:8]

ADC A

ADC B

(local)

Master

sync

enable

Disable

SDIO

pull-

down

Gain

enable

Force

gain

Default

Value

(Hex)

0x01

Ch A =

0x00

Ch B =

0x01

Comments

Disable the OR pin

for the indexed

channel

Assign an ADC

to an output

channel

0x01

0x88

0x00

0x02

0x00

Enables internal

oscillator for

clock rates of

<5 MHz

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Note, Interfacing to High Speed ADCs via SPI.

Sync Control (Register 0x100)

Bits[7:3]—Open

Bit 2—Clock Divider Next Sync Only

If the master sync enable bit (Address 0x100, Bit 0) and the

clock divider sync enable bit (Address 0x100, Bit 1) are high,

Bit 2 allows the clock divider to sync to the first sync pulse it

receives and to ignore the rest. The clock divider sync enable bit

(Address 0x100, Bit 1) resets after it syncs.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is

enabled when Bit 1 and Bit 0 are high, and the device is operating

in continuous sync mode as long as Bit 2 of the sync control is low.

Bit 0—Master Sync Enable

Bit 0 must be high to enable any of the sync functions.

USR2 (Register 0x101)

Bit 7—Enable OEB (Pin 47)

Normally set high, this bit allows Pin 47 to function as the output

enable. If this bit is set low, it disables Pin 47.

Bits [6:4]—Open

Bit 3—Enable GCLK Detect

Normally set high, this bit enables a circuit that detects encode

rates below ~5 MSPS. When a low encode rate is detected, an

internal oscillator, GCLK, is enabled to ensure the proper operation

of several circuits. If this bit is set low, the detector is disabled.

Bit 2—Run GCLK

This bit enables the GCLK oscillator. For some applications

with encode rates below 10 MSPS, it may be preferable to set

this bit high to supersede the GCLK detector.

Rev. 0 | Page 34 of 40

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