AD9572ACPZPEC-RL(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9572ACPZPEC-RL
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD9572ACPZPEC-RL Datasheet PDF : 20 Pages
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AD9572
THEORY OF OPERATION
REFSEL
VS
REFCLK
XTAL
OSC
1
0
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
VLDO
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
VLDO
AD9572
BYPASS1
VS GND
LDO
DIVIDE
BY 17
VCO
DIVIDE
BY 5
LDO
DIVIDE
BY 25
VCO
DIVIDE
BY 4
DIVIDE
BY 5
CMOS
25M
DIVIDE
BY 4
106.25MHz
LVPECL/
LVDS
106M
106M
106M
106M
BYPASS2
DIVIDE
BY 4
DIVIDE
BY 4
DIVIDE
BY 5
DIVIDE
BY 3
156.25MHz
LVPECL/
LVDS
125MHz/100MHz
0
1
LVPECL/
LVDS
LEVEL
DECODE
156M
156M
100M/125M
100M/125M
FREQSEL
125MHz/100MHz
0
1
LVPECL/
LVDS
33.33MHz
CMOS
100M/125M
100M/125M
33M
Figure 12. Detailed Block Diagram
FORCE_LOW
Figure 12 shows a block diagram of the AD9572. The chip
combines dual PLL cores, which are configured to generate the
specific clock frequencies required for networking applications,
without any user programming. This PLL is based on proven
Analog Devices synthesizer technology, noted for its exceptional
phase noise performance. The AD9572 is highly integrated and
includes loop filters, regulators for supply noise immunity, all
the necessary dividers with multiple output buffers in a choice
of formats, and a crystal oscillator. A user need only supply a
25 MHz reference clock or an external crystal to implement an
entire line card clocking solution
that does not require any processor intervention. A copy of
the 25 MHz reference source is also available.
OUTPUTS
Table 14 provides a summary of the outputs available.
Table 14. Output Formats
Frequency
25 MHz
106.25 MHz
156.25 MHz
100 MHz or 125 MHz
33.33 MHz
Format
CMOS
LVPECL/LVDS
LVPECL/LVDS
LVPECL/LVDS
CMOS
Copies
1
2
1
2
1
Note that the pins labeled 100M/125M can provide 100 MHz or
125 MHz by strapping the FREQSEL pin as shown in Table 15.
Rev. 0 | Page 14 of 20
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