AD9572ACPZPEC-RL(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9572ACPZPEC-RL
(Rev.:Rev0)

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

Analog Devices 

Table 15. FREQSEL (Pin 27) Definition

Frequency Available

from Pin 19 and Pin 20

FREQSEL (MHZ)

Frequency Available

from Pin 21 and Pin 22

(MHZ)

0

125

125

1

100

100

NC

125

100

3.5mA

OUT

OUTB

AD9572

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the reference clock and feedback

divider to produce an output proportional to the phase and

frequency difference between them. Figure 15 shows a

simplified schematic.

3.3V

HIGH

D1 Q1 UP

CHARGE

PUMP

REFCLK

CLR1

CP

3.5mA

Figure 13. LVDS Output Simplified Equivalent Circuit

The simplified equivalent circuits of the LVDS and LVPECL

outputs are shown in Figure 13 and Figure 14.

3.3V

OUT

OUTB

GND

Figure 14. LVPECL Output Simplified Equivalent Circuit

The differential outputs are factory programmed to either LVPECL

or LVDS format, and either option can be sampled on request.

CMOS drivers tend to generate more noise than differential

outputs and, as a result, the proximity of the 33.33 MHz output

to Pin 21 and Pin 22 does affect the jitter performance when

FREQSEL = 0 (that is, when the differential output is generating

125 MHz). For this reason, the 33 MHz pin can be forced to a

low state by asserting the FORCE_LOW signal on Pin 37 (see

Table 16). An internal pull-down enables the 33.33 MHz output

if the pin is not connected.

Table 16. FORCE_LOW (Pin 37) Definition

FORCE_LOW 33.33 MHz Output (Pin 23)

0 or NC

33.33 MHz

1

0

HIGH

FEEDBACK

DIVIDER

CLR2

D2 Q2

DOWN

GND

Figure 15. PFD Simplified Schematic

POWER SUPPLY

The AD9572 requires a 3.3 V ± 10% power supply for VS. The

tables in the Specifications section give the performance expected

from the AD9572 with the power supply voltage within this

range. The absolute maximum range of −0.3 V to +3.6 V, with

respect to GND, must never be exceeded on the VS pin.

Good engineering practice should be followed in the layout of

power supply traces and the ground plane of the PCB. The

power supply should be bypassed on the PCB with adequate

capacitance (>10 μF). The AD9572 should be bypassed with

adequate capacitors (0.1 μF) at all power pins as close as

possible to the part. The layout of the AD9572 evaluation board

is a good example.

The exposed metal paddle on the AD9572 package is an electrical

connection, as well as a thermal enhancement. For the device to

function properly, the paddle must be properly attached to ground

(GND). The PCB acts as a heat sink for the AD9572; therefore,

this GND connection should provide a good thermal path to a

larger dissipation area, such as a ground plane on the PCB.

CMOS CLOCK DISTRIBUTION

The AD9572 provides two CMOS clock outputs (one 25 MHz

and one 33.33 MHz) that are dedicated CMOS levels. Whenever

single-ended CMOS clocking is used, some of the following

general guidelines should be followed.

Point-to-point nets should be designed such that a driver has

one receiver only on the net, if possible. This allows for simple

termination schemes and minimizes ringing due to possible

mismatched impedances on the net. Series termination at the

source is generally required to provide transmission line

matching and/or to reduce current transients at the driver.

Rev. 0 | Page 15 of 20

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