AD9572ACPZPEC-RL(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9572ACPZPEC-RL
(Rev.:Rev0)

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

Analog Devices 

AD9572

The value of the resistor is dependent on the board design and

timing requirements (typically 10 Ω to 100 Ω is used). CMOS

outputs are limited in terms of the capacitive load or trace

length that they can drive. Typically, trace lengths less than

6 inches are recommended to preserve signal rise/fall times

and signal integrity.

CMOS

60.4Ω

10Ω 1.0 INCH

MICROSTRIP

5pF

GND

Figure 16. Series Termination of CMOS Output

Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the AD9572 do not supply enough current

to provide a full voltage swing with a low impedance resistive,

far-end termination, as shown in Figure 17. The far-end

termination network should match the PCB trace impedance

and provide the desired switching point. The reduced signal

swing may still meet receiver input requirements in some

applications. This can be useful when driving long trace lengths

on less critical nets.

VPULLUP = 3.3V

10Ω

50Ω

CMOS

100Ω

100Ω

5pF

Figure 17. CMOS Output with Far-End Termination

LVPECL CLOCK DISTRIBUTION

The low voltage, positive emitter-coupled logic (LVPECL)

outputs of the AD9572 provide the lowest jitter clock signals

available from the AD9572. The LVPECL outputs (because they

are open emitter) require a dc termination to bias the output

transistors. The simplified equivalent circuit in Figure 14 shows

the LVPECL output stage.

In most applications, a standard LVPECL far-end termination is

recommended, as shown in Figure 18. The resistor network is

designed to match the transmission line impedance (50 Ω) and

the desired switching threshold (1.3 V).

3.3V

3.3V

50Ω

127Ω

3.3V

127Ω

LVPECL

SINGLE-ENDED

(NOT COUPLED)

LVPECL

50Ω

VT = VCC – 1.3V

83Ω

83Ω

Figure 18. LVPECL Far-End Termination

3.3V

LVPECL

200Ω

0.1nF

DIFFERENTIAL

0.1nF (COUPLED)

100Ω

200Ω

3.3V

LVPECL

Figure 19. LVPECL with Parallel Transmission Line

LVDS CLOCK DISTRIBUTION

Low voltage differential signaling (LVDS) is a second

differential output option for the AD9572. LVDS uses a current

mode output stage with a factory programmed current level.

The normal value (default) for this current is 3.5 mA, which

yields a 350 mV output swing across a 100 Ω resistor. The LVDS

outputs meet or exceed all ANSI/TIA/EIA-644 specifications.

A recommended termination circuit for the LVDS outputs is

shown in Figure 20.

50Ω

LVDS

100Ω

LVDS

50Ω

Figure 20. LVDS Output Termination

See the AN-586 Application Note on the Analog Devices

website at www.analog.com for more information about LVDS.

REFERENCE INPUT

By default, the crystal oscillator is enabled and used as the

reference source, which requires the connection of an external

25 MHz crystal. The REFSEL pin is pulled high internally by

about 30 kΩ to support default operation. When REFSEL is tied

low, the crystal oscillator is powered down, and the REFCLK pin

must provide a good quality 25 MHz reference clock instead.

This single-ended input can be driven by either a dc-coupled

LVCMOS level signal or an ac-coupled sine wave or square

wave, provided that an external divider is used to bias the input

at VS/2.

Table 17. REFSEL (Pin 9) Definition

REFSEL

Reference Source

0

REFCLK input

1

Internal crystal oscillator

POWER AND GROUNDING CONSIDERATIONS AND

POWER SUPPLY REJECTION

Many applications seek high speed and performance under less

than ideal operating conditions. In these application circuits,

the implementation and construction of the PCB is as important

as the circuit design. Proper RF techniques must be used for

device selection, placement, and routing, as well as for power

supply bypassing and grounding to ensure optimum performance.

Rev. 0 | Page 16 of 20

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