AD9753-EB(Rev0) View Datasheet(PDF) - Analog Devices
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AD9753-EB Datasheet PDF : 26 Pages
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AD9753
source. For single-ended operation, CLK+ should be driven by
a logic source while CLK– should be set to the threshold voltage
of the logic source. This can be done via a resistor divider/
capacitor network as shown in Figure 15a. For differential opera-
tion, both CLK+ and CLK– should be biased to CLKVDD/2
via a resistor divider network as shown in Figure 15b.
RSERIES AD9753
CLK+
CLKVDD
0.1F
VTHRESHOLD
CLK–
CLKCOM
Figure 15a. Single-Ended Clock Interface
0.1F
0.1F
0.1F
AD9753
CLK+
CLKVDD
CLK–
CLKCOM
Figure 15b. Differential Clock Interface
Because the output of the AD9753 is capable of being updated
at up to 300 MSPS, the quality of the clock and data input sig-
nals are important in achieving the optimum performance. The
drivers of the digital data interface circuitry should be speci-
fied to meet the minimum setup-and-hold times of the AD9753
as well as its required min/max input logic level thresholds.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a low
value resistor network (i.e., 20 Ω to 100 Ω) between the AD9753
digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
data feedthrough. For longer run lengths and high data update
rates, strip line techniques with proper termination resistors
should be considered to maintain “clean” digital inputs.
The external clock driver circuitry should provide the AD9753
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a reconstructed
waveform. Thus, the clock input should be driven by the fastest
logic family suitable for the application.
Note that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies. Also,
at higher sampling rates, the 20% tolerance of the digital logic
threshold should be considered since it will affect the effective
clock duty cycle and, subsequently, cut into the required data
setup-and-hold times.
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9753 is rising edge triggered, and so
exhibits SNR sensitivity when the data transition is close to this
edge. In general, the goal when applying the AD9753 is to make
the data transition close to the falling clock edge. This becomes
more important as the sample rate increases. Figure 16 shows
the relationship of SNR to clock placement with different sample
rates. Note that the setup and hold times implied in Figure 16
appear to violate the maximums stated in the Digital Specifica-
tions of this data sheet. The variation in Figure 16 is due to the
skew present between data bits inherent in the digital data gen-
erator used to perform these tests. Figure 16 is presented to
show the effects of violating set up and hold times, and to show
the insensitivity of the AD9753 to clock placement when data
transitions fall outside of the so-called “bad window.” The setup
and hold times stated in the Digital Specifications were mea-
sured on a bit-by-bit basis, therefore eliminating the skew
present in the digital data generator. At higher data rates, it
becomes very important to account for the skew in the input
digital data when defining timing specifications.
80
70
60
50
40
30
20
10
0
–3
–2
–1
0
1
2
3
TIME OF DATA TRANSITION RELATIVE TO PLACEMENT OF
CLK RISING EDGE (ns), fOUT = 10MHz, fDAC = 300MHz
Figure 16. SNR vs. Time of Data Transition Relative to
Clock Rising Edge
POWER DISSIPATION
The power dissipation, PD, of the AD9753 is dependent on sev-
eral factors that include: (1) The power supply voltages (AVDD
and DVDD), (2) the full-scale current output IOUTFS, (3) the
update rate fCLOCK, and (4) the reconstructed digital input wave-
form. The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD
IAVDD is directly proportional to IOUTFS as shown in Figure 17,
and is insensitive to fCLOCK. Conversely, IDVDD is dependent on
both the digital input waveform, fCLOCK, and digital supply DVDD.
Figure 18 shows IDVDD as a function of the ratio (fOUT/fDAC) for
various update rates. In addition, Figure 19 shows the effect
that the speed of fDAC has on the PLLVDD current, given the
PLL divider ratio.
–14–
REV. 0
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