AD9753-EB(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9753-EB Datasheet PDF : 26 Pages
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AD9753
Pseudo Zero Stuffing/IF Mode
The excellent dynamic range of the AD9753 allows its use in
applications where synthesis of multiple carriers is desired. In
addition, the AD9753 can be used in a pseudo zero stuffing
mode which improves dynamic range at IF frequencies. In this
mode, data from the two input channels is interleaved to the
DAC, which is running at twice the speed of either of the input
ports. However, the data at Port 2 is held constant at midscale.
The effect of this is shown in Figure 33. The IF signal is the
image, with respect to the input data rate, of the fundamental.
Normally, the sinx/x response of the DAC will attenuate this
image. Zero stuffing improves the passband flatness so that the
image amplitude is closer to that of the fundamental signal.
Zero stuffing can be an especially useful technique in the syn-
thesis of IF signals.
0
–10
–20
AMPLITUDE
OF IMAGE
–30
WITHOUT
ZERO STUFFING
–40
AMPLITUDE
OF IMAGE
USING
ZERO STUFFING
–50
0
0.5
1
1.5
2
FREQUENCY – Normalized To Input Data Rate
Figure 33. Effects of Pseudo Zero Stuffing on Spectrum
of AD9753
A single-ended clock can be applied via J3. By setting the SE/
DIFF labeled jumpers J2, 3, 4, 6, the input clock can be directed
to the CLK+/CLK– inputs of the AD9753 in either a single-
ended or differential manner. If a differentially applied clock is
desired, a Mini-Circuits T1-1T transformer should be used in
the position of T2. Note that with a single-ended square wave
clock input, T2 must be removed. A clock can also be applied
via the ribbon cable on port 1 (P1), Pin 33. By inserting the
EDGE jumper (JP1), this clock will be applied to the CLK+
input of the AD9753. JP3 should be set in its SE position in this
application to bias CLK– to 1/2 the supply voltage.
The AD9753’s PLL clock multiplier can be enabled by inserting
JP7 in the IN position. As described in the Typical Performance
Characteristics and Functional Description sections, with the
PLL enabled, a clock at 1/2 the output data rate should be
applied as described in the last paragraph. The PLL takes care
of the internal 2× frequency multiplication and all internal tim-
ing requirements. In this application, the PLLLOCK output
indicates when lock is achieved on the PLL. With the PLL
enabled, the DIV0 and DIV1 jumpers (JP8 and JP9) provide the
PLL divider ratio as described in Table I.
The PLL is disabled when JP7 is in the EX setting. In this mode,
a clock at the speed of the output data rate must be applied to
the clock inputs. Internally, the clock is divided by 2. For data
synchronization, a 1× clock is provided on the PLLLOCK pin
in this application. Care should be taken to read the timing
requirements described earlier in the data sheet for optimum per-
formance. With the PLL disabled, the DIV0 and DIV1 jumpers
define the mode (interleaved, noninterleaved) as described in
Table II.
EVALUATION BOARD
The AD9753-EB is an evaluation board for the AD9753 TxDAC.
Careful attention to layout and circuit design, combined with
prototyping area, allows the user to easily and effectively evalu-
ate the AD9753 in different modes of operation.
Referring to Figures 34 and 35, the AD9753’s performance
can be evaluated differentially or single-endedly using either a
transformer, or directly coupling the output. To evaluate the
output differentially using the transformer, it is recommended
that either the Mini-Circuits T1-1T (through-hole) or the Coilcraft
TTWB-1-B (SMT) be placed in the position of T1 on the evalu-
ation board. To evaluate the output either single-ended or direct-
coupled, remove the transformer and bridge either BL1 or BL2.
The digital data to the AD9753 comes from two ribbon cables
that interface to the 40-lead IDC connectors P1 and P2. Proper
termination or voltage scaling can be accomplished by installing
the resistor pack networks RN1–RN12. RN1, 4, 7, 10 are 22 Ω
DIP resistor packs and should be installed as they help reduce the
digital edge rates and therefore peak current on the inputs.
–20–
REV. 0
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