AD9783-DPG2-EBZ View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9783-DPG2-EBZ

Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs

Analog Devices 

AD9780/AD9781/AD9783

Data Sheet

SPI REGISTER DESCRIPTIONS

Reading these registers returns previously written values for all defined register bits, unless otherwise noted.

Table 12.

Register

SPI Control

Data Control

Power-Down

Setup and Hold

Timing Adjust

Seek

Mix Mode

DAC1 FSC

Address Bit Name

Function

0x00

7 SDIO_DIR

0, operate SPI in 4-wire mode. The SDIO pin operates as an input only pin.

1, operate SPI in 3-wire mode. The SDIO pin operates as a bidirectional data line.

6 LSBFIRST

0, MSB first per SPI standard.

1, LSB first per SPI standard.

Only change LSB/MSB order in single-byte instructions to avoid erratic behavior

due to bit order errors.

5 RESET

0, execute software reset of SPI and controllers, reload default register values

except Register 0x00.

1, set software reset, write 0 on the next (or any following) cycle to release the reset.

0x02

7 DATA

0, DAC input data is twos complement binary format.

1, DAC input data is unsigned binary format.

4 INVDCO

1, inverts the data clock output. Used for adjusting timing of input data.

0x03

7 PD_DCO

1, power down data clock output driver circuit.

6 PD_INPT

1, power down input.

5 PD_AUX2

1, power down AUX2 DAC

4 PD_AUX1

1, power down AUX1 DAC.

3 PD_BIAS

1, power down voltage reference bias circuit.

2 PD_CLK

1, power down DAC clock input circuit.

1 PD_DAC2

1, power down DAC2.

0 PD_DAC1

1, power down DAC1.

0x04

7:4 SET[3:0]

4-bit value used to determine input data setup timing.

3:0 HLD[3:0]

4-bit value used to determine input data hold timing.

0x05

4:0 SAMP_DLY[4:0] 5-bit value used to optimally position input data relative to internal sampling clock.

0x06

2 LVDS low

1 LVDS high

One of the LVDS inputs is above the input voltage limits of the IEEE reduced link

specification.

One of the LVDS inputs is below the input voltage limits of the IEEE reduced link

specification.

0 SEEK

Indicator bit used with LVDS_SET and LVDS HLD to determine input data timing

margin.

0x0A

3:2 DAC1MIX[1:0]

00, selects normal mode, DAC1.

01, selects return-to-zero mode, DAC1.

10, selects return-to-zero mode, DAC1.

11, selects mix mode, DAC1.

1:0 DAC2MIX[1:0] 00, selects normal mode, DAC2.

01, selects return-to-zero mode, DAC2.

10, selects return-to-zero mode, DAC2.

11, selects mix mode, DAC2.

0x0B

0x0C

7:0 DAC1FSC[9:0]

1:0

DAC1 full-scale 10-bit adjustment word.

0x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA.

0x200, sets DAC full-scale output current to the nominal value of 20.0 mA.

0x000, sets DAC full-scale output current to the minimum value of 8.66 mA.

Rev. B | Page 22 of 32

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