AD9783-DPG2-EBZ View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9783-DPG2-EBZ

Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs

Analog Devices 

AD9780/AD9781/AD9783

SPI PORT, RESET, AND PIN MODE

In general, when the AD9780/AD9781/AD9783 are powered

up, an active high pulse applied to the RESET pin should follow.

This ensures the default state of all control register bits. In

addition, once the RESET pin goes low, the SPI port can be

activated; thus, CSB should be held high.

For applications without a controller, the AD9780/AD9781/

AD9783 also supports pin mode operation, which allows some

functional options to be pin selected without the use of the SPI

port. Pin mode is enabled anytime the RESET pin is held high.

Data Sheet

In pin mode, the four SPI port pins take on secondary

functions, as shown in Table 13.

Table 13. SPI Pin Functions (Pin Mode)

Pin

Name Pin Mode Function

SDIO

DATA (Register 0x02, Bit 7), bit value (1/0) equals pin

state (high/low).

CSB

Enable mix mode. If CSB is high, Register 0x0A is set

to 0x05, putting both DAC1 and DAC2 into mix mode.

SDO

Enable full power-down. If SDO is high, Register 0x03

is set to 0xFF.

Rev. B | Page 24 of 32

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