AD9985ABSTZ-110 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9985ABSTZ-110 Datasheet PDF : 32 Pages
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AD9985A
COAST TIMING
In most computer systems, the Hsync signal is provided
continuously on a dedicated wire. In these systems, the Coast
input and function are unnecessary and should not be used, and
the pin should be permanently connected to the inactive state.
In some systems, however, Hsync is disturbed during the
vertical sync period (Vsync). In some cases, Hsync pulses
disappear. In other systems, such as those that use composite
sync (Csync) signals or embedded sync-on-green (SOG), Hsync
includes equalization pulses or other distortions during Vsync.
To avoid upsetting the clock generator during Vsync, it is
important to ignore these distortions. If the pixel clock PLL
detects extraneous pulses, it attempts to lock to this new
frequency, and changes frequency by the end of the Vsync
period. It then takes a few lines of correct Hsync timing to
recover at the beginning of a new frame, resulting in a tearing of
the image at the top of the display.
The Coast input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and allows the
clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PxCK
HS
ADCCK
5-PIPE DELAY
DATACK
DOUTA
HSOUT
.
D0 D1 D2 D3 D4 D5 D6 D7
VARIABLE DURATION
Figure 10. 4:4:4 Mode (For RGB and YUV)
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PxCK
HS
ADCCK
5-PIPE DELAY
DATACK
GOUTA
ROUTA
HSOUT
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
U0 V1 U2 V3 U4 V5 U6 V7
VARIABLE DURATION
Figure 11. 4:2:2 Mode (For YUV Only)
Rev. 0 | Page 16 of 32
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