AD9985ABSTZ-110 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9985ABSTZ-110

110 MSPS/140 MSPS Analog Interface for Flat Panel Displays

Analog Devices 

AD9985A

Write and

Hexadecimal Read or

Default

Address

Read-Only Bits Value

Register

Name

Function

*1******

Bit 6—Clamp Polarity. Valid only with external clamp signal.

(Logic 0 = active high, Logic 1 selects active low.)

**0*****

Bit 5—Coast Select. Logic 0 selects the COAST input pins to be used

for the PLL coast. Logic 1 selects Vsync to be used for the PLL coast.

***0****

Bit 4—Coast Polarity Override. (Logic 0 = polarity determined by

chip, Logic 1 = polarity set by Bit 3 in Register 0x0F.)

****1***

Bit 3—Coast Polarity. Selects polarity of external Coast signal

(Logic 0 = active low, Logic 1 = active high).

*****1**

Bit 2—Seek Mode Override (Logic 1 = allow low power mode,

Logic 0 = disallow low power mode).

******1*

Bit 1—PWRDN. Full Chip Power-Down, Active Low (Logic 0 = full chip

power-down, Logic 1 = normal).

0x10

R/W

7:3 10111*** Sync-on-Green Sync-on-Green Threshold. Sets the voltage level of the sync-on-

Threshold

green slicer’s comparator.

*****0**

Bit 2—Red Clamp Select. Logic 0 selects clamp to ground. Logic 1

selects clamp to midscale (voltage at Pin 37).

******0*

Bit 1—Green Clamp Select. Logic 0 selects clamp to ground. Logic 1

selects clamp to midscale (voltage at Pin 37).

*******0

Bit 0— Blue Clamp Select. Logic 0 selects clamp to ground. Logic 1

selects clamp to midscale (voltage at Pin 37).

0x11

R/W

7:0 00100000 Sync Separator Sync Separator Threshold. Sets the number of internal 5 MHz clock

Threshold

periods the sync separator counts to before toggling high or low.

This should be set to some number greater than the maximum Hsync

or equalization pulse width.

0x12

R/W

7:0 00000000 Pre-Coast

Pre-Coast. Sets the number of Hsync periods that Coast becomes

active prior to Vsync.

0x13

R/W

7:0 00000000 Post-Coast

Post-Coast. Sets the number of Hsync periods that Coast stays active

following Vsync.

0x14

RO

7:0

Sync Detect

Bit 7—Hsync detect. It is set to Logic 1 if Hsync is present on the

analog interface; otherwise it is set to Logic 0.

Bit 6—AHS: Active Hsync. This bit indicates which analog Hsync is

being used (Logic 0 = Hsync input pin, Logic 1 = Hsync from

sync-on-green).

Bit 5—Input Hsync Polarity Detect (Logic 0 = active low,

Logic 1 = active high).

Bit 4—Vsync Detect. It is set to Logic 1 if Vsync is present on the

analog interface; otherwise it is set to Logic 0.

Bit 3—AVS: Active Vsync. This bit indicates which analog Vsync is

being used (Logic 0 = Vsync input pin, Logic 1 = Vsync from

sync separator).

Bit 2—Output Vsync Polarity Detect (Logic 0 = active low,

Logic 1 = active high).

Bit 1—Sync-on-Green Detect. It is set to Logic 1 if sync is present on

the green video input; otherwise it is set to 0.

Bit 0—Input Coast Polarity Detect (Logic 0 = active low,

Logic 1 = active high).

0x15

R/W

7:2 111111** Reserved

Bits [7:2] Reserved for future use. Must be written to 111111 for

proper operation.

1 ******1* Output

Formats

Bit 1—4:2:2 Output Formatting Mode (Logic 0 = 4:2:2 mode,

Logic 1= 4:4:4 mode).

0 *******1 Reserved

Bit 0—Must be set to 0 for proper operation.

Rev. 0 | Page 18 of 32

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