AD9985ABSTZ-110 View Datasheet(PDF) - Analog Devices
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AD9985ABSTZ-110 Datasheet PDF : 32 Pages
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Table 24. Coast Input Polarity Override Settings
Override
Result
0
Determined by chip (power-up default)
1
Determined by user
0F
3 Coast Input Polarity
This bit indicates the polarity of the Coast signal that
is applied to the PLL COAST input.
Table 25. Coast Input Polarity Settings
Coast Polarity Result
0
Active low
1
Active high (power-up default)
Active low means that the clock generator ignores
Hsync inputs when Coast is low, and continues
operating at the same nominal frequency until Coast
goes high.
Active High means that the clock generator ignores
Hsync inputs when Coast is high, and continues
operating at the same nominal frequency until Coast
goes low.
This function needs to be used along with the Coast
polarity override bit (Bit 4).
0F
2 Seek Mode Override
This bit is used to either allow or disallow the low
power mode. The low power mode (seek mode)
occurs when there are no signals on any of the Sync
inputs.
Table 26. Seek Mode Override Settings
Override
Result
1
Allow seek mode (power-up default)
0
Disallow seek mode
0F
1 PWRDN
This bit is used to put the chip in full power-down. See
the Power Management section for details on which
blocks are powered down.
Table 27. Power-Down Settings
Power-Down Result
0
Power-down
1
Normal operation
10
7-3 Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the
sync-on-green slicer to be adjusted. This register
adjusts it in steps of 10 mV, with the minimum setting
equaling 10 mV (11111) and the maximum setting
equaling 330 mV (00000).
The default setting is 23, which corresponds to a
threshold value of 100 mV; for a threshold of 150 mV,
the setting should be 18.
AD9985A
10
2 Red Clamp Select
This bit determines whether the red channel is
clamped to ground or to midscale. For RGB video, all
three channels are referenced to ground. For YCbCr
(or YUV), the Y channel is referenced to ground, but
the CbCr channels are referenced to midscale.
Clamping to midscale actually clamps to Pin 37.
Table 28. Red Clamp Select Settings
Clamp
Result
0
Clamp to ground (power-up default)
1
Clamp to midscale (Pin 37)
10
1 Green Clamp Select
This bit determines whether the green channel is
clamped to ground or to midscale.
Table 29. Green Clamp Select Settings
Clamp
Result
0
Clamp to ground (power-up default)
1
Clamp to midscale (Pin 37)
10
0 Blue Clamp Select
This bit determines whether the blue channel is
clamped to ground or to midscale.
Table 30. Blue Clamp Select Settings
Clamp
Result
0
Clamp to ground (power-up default)
1
Clamp to midscale (Pin 37)
11
7–0 Sync Separator Threshold
This register is used to set the responsiveness of the
sync separator. It sets the number of internal 5 MHz
clock periods the sync separator must count to before
toggling high or low. It works like a low-pass filter to
ignore Hsync pulses in order to extract the Vsync
signal. This register should be set to some number
greater than the maximum Hsync pulse width. The
sync separator threshold uses an internal dedicated
clock with a frequency of approximately 5 MHz.
The default for this register is 32.
12
7–0 Pre-Coast
This register allows the Coast signal to be applied
prior to the Vsync signal. This is necessary in cases
where pre-equalization pulses are present. The step
size for this control is one Hsync period.
The default is 0.
13
7–0 Post-Coast
This register allows the Coast signal to be applied
following the Vsync signal. This is necessary when
post-equalization pulses are present. The step size for
this control is one Hsync period.
The default is 0.
Rev. 0 | Page 23 of 32
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