AD9985A
Serial Interface Read/Write Examples
Write to one control register:
1. Start signal
2. Slave address byte (R/W Bit = low)
3. Base address byte
4. Data byte to base address
5. Stop signal
Write to four consecutive control registers:
1. Start signal
2. Slave address byte (R/W bit = low)
3. Base address byte
4. Data byte to base address
5. Data byte to (base address + 1)
6. Data byte to (base address + 2)
7. Data byte to (base address + 3)
8. Stop signal
Read from one control register:
1. Start signal
2. Slave address byte (R/W bit = low)
3. Base address byte
4. Start signal
5. Slave address byte (R/W bit = high)
6. Data byte from base address
7. Stop signal
Read from four consecutive control registers:
1. Start signal
2. Slave address byte (R/W bit = low)
3. Base address byte
4. Start signal
5. Slave address byte (R/W Bit = high)
6. Data byte from base address
7. Data byte from (base address + 1)
8. Data byte from (base Address + 2)
9. Data byte from (base Address + 3)
10. Stop signal
SDA
SCL
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ACK
Figure 13. Serial Interface—Typical Byte Transfer
SOG
HSYNC IN
SYNC STRIPPER
NEGATIVE PEAK
CLAMP
ACTIVITY
DETECT
COAST
VSYNC IN
ACTIVITY
DETECT
POLARITY
DETECT
ACTIVITY
DETECT
COMP
SYNC
MUX 1
SYNC SEPARATOR
INTEGRATOR
1/S
VSYNC
SOG OUT
PLL
POLARITY
DETECT
HSYNC
MUX 2
COAST
CLOCK
GENERATOR
HSYNC OUT
PIXEL CLOCK
HSYNC OUT
MUX 3
POLARITY
DETECT
AD9985A
MUX 4
VSYNC OUT
Figure 14. Sync Processing Block Diagram
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