AD9985ABSTZ-110 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9985ABSTZ-110 Datasheet PDF : 32 Pages
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AD9985A
14
7 Hsync Detect
This bit is used to indicate when activity is detected on
the Hsync input pin (Pin 30). If Hsync is held high or
low, activity will not be detected.
Table 34. Vsync Detection Results
Detect
Result
0
No activity detected
1
Activity detected
Table 31. Hsync Detection Results
Detect
Function
0
No activity detected
1
Activity detected
The sync processing block diagram (Figure 14) shows
where this function is implemented.
14
6 Active Hsync (AHS)
This bit indicates which Hsync input source is being
used by the PLL (Hsync input or sync-on-green).
Bit 7 and Bit 1 in this register determine which source
is used. If both Hsync and SOG are detected, the user
can determine which has priority via Bit 3 in
Register 0x0E. The user can override this function via
Bit 4 in Register 0x0E. If the override bit is set to
Logic 1, then this bit is set to the state of Bit 3 in
Register 0x0E.
Table 32. Active Hsync Results
Bit 7
Bit 1
Bit 4
(Hsync
(SOG
Reg. 0x0E
Detect)
Detect)
(Override)
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
AHS
Bit 3 in 0x0E
1
0
Bit 3 in 0x0E
Bit 3 in 0x0E
AHS = 0 means use the Hsync pin input for Hsync.
AHS = 1 means use the SOG pin input for Hsync.
The sync processing block diagram (Figure 14) shows
where this function is implemented.
14
3 Active Vsync (AVS)
This bit indicates which Vsync source is being used,
the Vsync input or output from the sync separator.
Bit 4 in this register determines which is active. If both
Vsync and SOG are detected, the user can determine
which has priority via Bit 0 in Register 0x0E. The user
can override this function via Bit 1 in Register 0x0E. If
the override bit is set to Logic 1, this bit is set to the
state of Bit 0 in Register 0x0E.
Table 35. Active Vsync Results
Bit 4, Reg 14H
(Vsync Detect)
Bit 1, Reg. 0x 0E
(Override)
1
0
0
0
X
1
AVS = 0 means Vsync input.
AVS
0
1
Bit 0 in 0x0E
AVS = 1 means Sync separator.
The override bit is in Register 0x0E, Bit 1.
14
2 Detected Vsync Output Polarity Status
This bit reports the status of the Vsync output polarity
detection circuit. It can be used to determine the
polarity of the Vsync output. The detection circuit’s
location is shown in the sync processing block
diagram (Figure 14).
Table 36. Detected Vsync Output Polarity Status
The override bit is in Register 0x0E, Bit 4.
Vsync Polarity
Status
Result
14
5 Detected Hsync Input Polarity Status
This bit reports the status of the Hsync input polarity
detection circuit. It can be used to determine the
polarity of the Hsync input. The detection circuit’s
location is shown in the sync processing block
diagram (Figure 14).
Table 33. Detected Hsync Input Polarity Status
Hsync Polarity Status
Result
0
Negative
1
Positive
14
4 Vsync Detect
0
Active low
1
Active high
14
1 Sync-on-Green Detect
This bit is used to indicate when sync activity is
detected on the sync-on-green input pin (Pin 49).
Table 37. Sync-on-Green Detection Results
Detect
Result
0
No activity detected
1
Activity detected
The sync processing block diagram (Figure 14) shows
where this function is implemented.
This bit is used to indicate when activity is detected on
the Vsync input pin (Pin 31). If Vsync is held steady
high or low, activity is not detected.
14
0 Detected Coast Polarity Status
This bit reports the status of the Coast input polarity
detection circuit. It can be used to determine the
polarity of the Coast input. The detection circuit’s
location is shown in the sync processing block
diagram (Figure 14).
Rev. 0 | Page 24 of 32
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