ADE3700
Register Name
SCL_ORIGHPOS_0
SCL_ORIGHPOS_1
SCL_ORIGHPOS_2
SCL_ORIGHPOS_3
SCL_ORIGVPOS_E_0
SCL_ORIGVPOS_E_1
SCL_ORIGVPOS_E_2
SCL_ORIGVPOS_E_3
SCL_THRES_SLOPE
SCL_THRES_OFFSET_L
SCL_THRES_OFFSET_H
SCL_CBBYPASS
SCL_CON_CAL_SEL
SCL_TESTCON
SCL_LUT1
SCL_LUT2
SCL_LUT3
SCL_LUT4
SCL_LUT5
SCL_LUT6
LCD Scaler
Table 15: LCD Scaler Registers (Sheet 2 of 3)
Addr
0x0A0A
0x0A0B
0x0A0C
0x0A0D
0x0A0E
0x0A0F
0x0A10
0x0A11
0x0A16
0x0A17
0x0A18
0x0A19
0x0A1A
0x0A1B
0x0A1C
0x0A1D
0x0A1E
0x0A1F
0x0A20
0x0A21
Mode Bits
R/W
[7:0]
R/W
[7:0]
R/W
[7:0]
RW
[2:0]
R/W
[7:0]
R/W
[7:0]
R/W
[7:0]
R/W
[2:0]
[7:6]
R/W
[5:0]
R/W
[7:0]
[7:2]
R/W
[1:0]
R/W
[7:2]
[1]
R/W
[0]
[7:1]
R/W
[0]
[7:2]
R/W
[1:0]
R/W
[7:0]
R/W
[7:0]
R/W
[7:0]
R/W
[7:0]
R/W
[7:0]
R/W
[7:0]
Default
Description
0x0
2’s complement, signed number 27-bit
horizontal position of the first output pixel
0x0
=(-dest_hpos * scalefactor_h) >> 5
0x0
0x0
0x0
2’s complement, signed number 27-bit
vertical position of the first output pixel of
the even frame = (-dest_vpos_e *
0x0
scalefactor_v) >> 5
0x0
0x28
0x40
0x0
0x2
0x0
0x0
0x0
0x0
0x0
0xFA
0xF7
0xF7
0xFC
0x2
0x0D
Reserved
Slope of the contrast amplification function
Offset of the contrast amplification function
[7:0]
Reserved
Offset of the contrast amplification function
[9:8]
Reserved
0: Normal
1: TCON control of contrast amplification
0: Contrast Amplification enabled
1: Bypass Contrast Amplification
Reserved
0: Context = max of RGB pk-pk
1: Context = sum of RGB pk-pk
6-bit contrast amplification test data
0x0, 0x3: normal
0x1: force input data into the contrast
amplification function to bits [7:2]
0x2: force the output context data to be bits
[5:2]
Sigmoidal Function LUT Entry 1, 8-bit 2’s
complement
Sigmoidal Function LUT Entry 2, 8-bit 2’s
complement
Sigmoidal Function LUT Entry 3, 8-bit 2’s
complement
Sigmoidal Function LUT Entry 4, 8-bit 2’s
complement
Sigmoidal Function LUT Entry 5, 8-bit 2’s
complement
Sigmoidal Function LUT Entry 6, 8-bit 2’s
complement
43/89