ADE3700XT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3700XT Datasheet PDF : 89 Pages
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ADE3700
Output Multiplexer
2.19.1 Sub Block Function
2.19.1.1 Right Shift
q shifts right from 0 to 4 positions, fills from the top with zeroes
q out_mux_ctrl1[2:0]
2.19.1.2 Byte Flip
q flips data bits in a byte from LSB to MSB, i.e. out[7:0] = in[0:7]
q out_mux_ctrl0[4]
2.19.1.3 Red & Blue Swap
q swaps red and blue channels, i.e. out[23:0] = {in[7:0],in[15:8],in[23:16]}
q out_mux_ctrl0[3]
2.19.1.4 Single to Double Wide Converter
q in Single Wide mode (out_mux_ctrl0[1] = 0)
— flops all data into either A or B channels depending on out_mux_ctrl0[2]
— either inv_a or inv_b is active depending on active channel
q in Double Wide mode (out_mux_ctrl0[1] = 1)
— flops data into A/B or B/A positions depending on out_mux_ctrl0[2].
— divides clock by 2 (hclk = half speed DCLK), resyncing each line with data enable
— output data transitions as posedge/negedge as set in out_mux_ctrl0[5]
— can handle odd output htotal (i.e. all divide by 2’s and state machines must be resynced per
line)
2.19.1.5 Data Inversion
q resyncs at the end of each line to inactive state with data enable falling edge −
q invert is possible on the first pixel – compares 1st pixel to blanking value
q compares subsequent 24-bit/48-bit data to the last output; if more bits flip (i.e. hamming
distance > active_bit_width/2), invert data word and toggle invert pin
q counts only active bits in hamming distance as determined by right shift and bit flip settings;
zeroes out non active data signals at output
q controls:
— out_mux_ctrl1[4]
- A and B channels have separate independent
- A and B channels treated as one 48-bit channel, inv_a = inv_b
— out_mux_ctrl1[5]
- data invert output polarity
— out_mux_ctrl1[6]
- data invert enable
q data invert pins can also be driven by tcon srtd[26] and srtd[27] for panel balancing
(out_mux_ctrl2[6] and out_mux_ctrl2[7])
q data can be inverted at the front end of the data inversion detection using tcon signals, either
separate or combined channels (out_mux_ctrl3[0])
2.19.1.6 Output Mux / Reg
q combines all signals to form the desired outputs
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