ADE3700
Table 27: Output Mux Specification (Sheet 2 of 2)
Output Multiplexer
ORA0
OBB7
OBB6
OBB5
OBB4
OBB3
OBB2
OBB1
OBB0
OGB7
OGB6
OGB5
OGB4
OGB3
OGB2
OGB1
OGB0
ORB7
ORB6
ORB5
ORB4
ORB3
ORB2
ORB1
ORB0
0
0 RDA0 PWMB RDA0 RDA0 RDA0 TCI8 RDA0 RDA0 TCI11
0
0 PWMA BDB7 BDB7 BDB7 BDB7 BDB7 BDB7 TCI10 BDB7
0
0 PWMB BDB6 BDB6 BDB6 BDB6 BDB6 BDB6 BDB6 BDB6
0
0 BDB5 BDB5 BDB5 BDB5 BDB5 BDB5 BDB5 BDB5 BDB5
0
0 BDB4 BDB4 BDB4 BDB4 BDB4 BDB4 BDB4 BDB4 BDB4
0
0 BDB3 BDB3 BDB3 BDB3 BDB3 BDB3 BDB3 BDB3 BDB3
0
0 BDB2 BDB2 BDB2 BDB2 BDB2 BDB2 BDB2 BDB2 BDB2
0
0 BDB1 BDB1 BDB1 BDB1 BDB1 BDB1 BDB1 BDB1 BDB1
0
0 BDB0 BDB0 BDB0 BDB0 BDB0 BDB0 BDB0 BDB0 TCI10
0
0 GDB7 GDB7 GDB7 GDB7 GDB7 GDB7 GDB7 TCI9 GDB7
0
0 GDB6 GDB6 GDB6 GDB6 GDB6 GDB6 GDB6 GDB6 GDB6
0
0 GDB5 GDB5 GDB5 GDB5 GDB5 GDB5 GDB5 GDB5 GDB5
0
0 GDB4 GDB4 GDB4 GDB4 GDB4 GDB4 GDB4 GDB4 GDB4
0
0 GDB3 GDB3 GDB3 GDB3 GDB3 GDB3 GDB3 GDB3 GDB3
0
0 GDB2 GDB2 GDB2 GDB2 GDB2 GDB2 GDB2 GDB2 GDB2
0
0 GDB1 GDB1 GDB1 GDB1 GDB1 GDB1 GDB1 GDB1 GDB1
0
0 GDB0 GDB0 GDB0 GDB0 GDB0 GDB0 GDB0 GDB0 TCI9
0
0 RDB7 RDB7 RDB7 RDB7 RDB7 RDB7 RDB7 TCI8 RDB7
0
0 RDB6 RDB6 RDB6 RDB6 RDB6 RDB6 RDB6 RDB6 RDB6
0
0 RDB5 RDB5 RDB5 RDB5 RDB5 RDB5 RDB5 RDB5 RDB5
0
0 RDB4 RDB4 RDB4 RDB4 RDB4 RDB4 RDB4 RDB4 RDB4
0
0 RDB3 RDB3 RDB3 RDB3 TCI11 RDB3 RDB3 RDB3 RDB3
0
0 RDB2 RDB2 RDB2 RDB2 TCI10 RDB2 RDB2 RDB2 RDB2
0
0 RDB1 RDB1 RDB1 RDB1 TCI9 RDB1 RDB1 RDB1 RDB1
0
0 RDB0 RDB0 RDB0 RDB0 TCI8 RDB0 RDB0 RDB0 TCI8
tci13 = tcon_in13, orb7 = output red B channel bit 7, rda3 = red A channel bit 3, etc. pwma = pwm_a
input.
Table 28: CLK_OUT Mux Specification
enable data
double
clk invert
OUT_MUX_CTRL0[0]
OUT_MUX_CTRL0[1]
OUT_MUX_CTRL0[5]
CLK_OUT
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
0
DOTCLK !DOTCLK HCLK
!HCLK
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