ADE3700XT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3700XT Datasheet PDF : 89 Pages
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ADE3700
Output Multiplexer
Table 31: RSDS Mode Specifications (Continued)
RSDS Time
t+2
t+3
clk_o
0
1
hsync_o o[r,g,b][a,b](2n)
1
bit from 2n
0
bit from 2n+1
o[r,g,b][a,b](2n+1)
!bit from 2n
!bit from 2n+1
Note: hsync_o is the positive clock signal according to the RSDS definition.
2.19.3 Per Pin Delay
Each of the 60 outputs has a per pin programmable delay. The delay is calibrated on the fly to the
XCLK period, which is assumed to be 37ns. Each pin can be delayed by up to 6ns in 0.4ns
increments. Code 0x0 is the least delay, code 0xF is the maximum delay. The setting is accurate to
±0.8ns across PVT. The calibration and resetting is done once per frame after the falling edge of
vertical enable to prevent glitches from delay mux changes in the active data period. The delays are
active in RSDS and normal output modes if enabled in the OUT_MUX_CTRL2 register.
Table 32: Output Mux Registers (Sheet 1 of 4)
Register Name
OMUX_CTRL_0
OMUX_CTRL_1
Addr
0x0C30
0x0C31
Mode Bits
R/W
[7]
R/W
[6:4]
R/W
[3]
R/W
[2]
R/W
[1]
R/W
[0]
R/W
[7]
R/W
[6]
R/W
[5]
R/W
[4]
R/W
[3]
R/W
[2]
R/W
[1]
R/W
[0]
Default
Description
0x0
in 2 ppc,
0: data invert for A+B comb.
1: data invert A/B separate
0x0
0x0 - 0x4: right shift per 8-bit R/G/B
0x5 - 0x7: Reserved
0x0
0: normal
1: flip msbs to lsbs
0x0
0: normal
1: swap R and B data
0x0
0: in 1 ppc, A channel active
0: in 2 ppc, Left on A, Right on B
1: in 1 ppc, B channel active
1: 2ppc, Left on B, Right on A
0x0
0: single wide, one pix/clk (ppc)
1: double wide, two pix/clk
0x0
Vsync Output Polarity
0x0
Hsync Output Polarity
0x0
Data Enable Output Polarity
0x0
Clock Output Invert
0x0
Data Invert Output Polarity
0x0
Data Invert Enable
0x0
0: TCON outputs set to zero
1: TCON outputs active
0x0
0: all data outputs set to zero
1: output enabled
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