ADE3000SX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3000SX

LCD Display Engines with Integrated DVI, ADC and YUV Ports

STMicroelectronics 

ADE3XXX

2 ADE3XXX Functional Description

Global Control Block

2.1 Global Control Block

The global control block is responsible for:

q Selecting Clock Sources

q Power Control

q I²C Control

q SCLK Frequency Synthesizer Control

q Block-by-Block Synchronous Reset Generation

The global control block runs on the XCLK clock domain which is required to be active for

programming. The clock domains of all other blocks are set in the Global Control Block. For I²C

access, the requested block must be driven with a valid clock above 10 MHz. Clock domains are

shown in Figure 2.

Figure 2: Clock Domains

Microcontroller

SCL, SDA

YUV Video

YUV, YUVCLK

DVI Link

RX0-2, RXC

PC Analog

INR, G, B

V,H,CSYNC

I2C

Global

PWM

XCLK

domain

Sync

Measure

Sync

Re-Time

YUV to RGB data

DVI Rx (Analog)

SMUX

DVI Decoder

HDCP

data

ADC (Analog)

DMUX

ADC Digital I/F

data

Data

Measure

Line Lock

PLL

INCLK

domain

ADE3XXX

Flicker

Detect

Scaler

SCLK

Freq.Synth.

SCLK

domain

Output

Sequencer

TCON

DOTCLK

domain

FM Freq.

Synth.

ORA, OGA, OBA

ORB, OGB, OBB

OCLK

ODE, OHS, OVS

TCON

To program the SCLK frequency synthesizer to a desired frequency (fout, in MHz), the following

equations apply:

Table 3: SCLK Frequency Ranges

Frequency Range

fOUT < 8 x fXCLK AND fOUT ≥ 4 x fXCLK

fOUT < 4 x fXCLK AND fOUT ≥ 2 x fXCLK

fOUT < 2 x fXCLK AND fOUT ≥ fXCLK

SDIV

0

1

2

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