Global Control Block
Table 3: SCLK Frequency Ranges (Continued)
Frequency Range
fOUT < fXCLK AND fOUT ≥ fXCLK /2
fOUT < fXCLK/2 AND fOUT ≥ fXCLK /4
fOUT < fXCLK/4 AND fOUT ≥ fXCLK /8
fOUT < fXCLK/8 AND fOUT ≥ fXCLK /16
fOUT < fXCLK/16 AND fOUT ≥ fXCLK /32
SDIV
3
4
5
6
7
ADE3XXX
MD = INT(fXCLK x (2(6 + NDIV - SDIV)) / fOUT)
PE = INT((215) x (MD + 1 - fXCLK x (2(6 + NDIV - SDIV)) / fOUT))
gwehneereraftXeCdLbKyisththisebeloxctekrnisaflXcTrAyLstxal2f(r2e+qNuDeIVn)c. y in MHz (typically 27). The maximum SCLK frequency
For lower power operation, set all clock sources to the “zero” setting and also set the analog power
disables. In this condition, only the crystal clock domain (XCLK) runs and blocks in INCLK or
DOTCLK domains are not accessible by I2C.
To detect a DVI plug event and wake from a low power state, program the DVI detection clock
source select to the DVI detect clock and enable the analog power control for the DVI detect clock.
All other clock sources are set to zero.
Table 4: Global Registers (Sheet 1 of 4)
Register Name
GLBL_NULL_ADDR
GLBL_CLK_SRC_SEL_0
Addr.
0x0000
0x0001
Mode
R/W
R/W
R/W
Bits
[7:0]
[7]
[6:4]
[3:0]
Default
Description
0x0 Chip Revision ID
0x0 Reserved
0x5 DOTCLK source
0x0: YUVCLK pin
0x1: SCLK freq synth
0x2: FM freq synth (normal)
0x3: INCLK
0x4: CLKIN pin
0x5: crystal clock
0x6: 0
0x7: Reserved
0xA INCLK source
0x0: YUVCLK pin (YUV Input)
0x1: DVI_PLLCLK (DVI Input)
0x2: ADCclock red
0x3: ADCclock green
0x4: ADC clock blue
0x5: SCLK freq synth
0x6: DVI detect clock
0x7: LLK PLL (ADC Input)
0x8: CLKIN pin
0x9: FM freq synth
0xA: crystal clock
0xB: 0
0xC - 0xF: Reserved
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