ADE3000SX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3000SX Datasheet PDF : 88 Pages
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ADE3XXX
Register Name
GLBL_CLK_SRC_SEL_3
GLBL_IK_SRST
GLBL_DK_SRST
FM Frequency Synthesizer
Table 4: Global Registers (Sheet 4 of 4)
Addr.
0x0012
Mode
R/W
R/W
0x0020 R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0040
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits
[7]
[6:4]
[3]
[2:0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Default
Description
Reserved
0x4 YUV clock source
0x0: YUVCLK pin
0x1: SCLK freq synth
0x2: YUVCLK pin (normal)
0x3: CLKIN pin
0x4: crystal clock
0x5: 0
0x6 - 0x7: Reserved
Reserved
0x4 DVI detection clock source
0x0: YUVCLK pin
0x1: SCLK freq synth
0x2: DVI detect clock (normal)
0x3: CLKIN pin
0x4: crystal clock
0x5: 0
0x6 - 0x7: Reserved
0x0 HDCP block reset synchronous to INCLK
0x0 DFT block reset synchronous to INCLK
0x0 ADC block reset synchronous to INCLK
0x0 SCALER block reset synchronous to INCLK
0x0 YUV block reset synchronous to INCLK
0x0 DVI block reset synchronous to INCLK
0x0 DMEAS block reset synchronous to INCLK
0x0 SMUX block reset synchronous to INCLK
0x0 Reserved
0x0 PGEN block reset synchronous to DOTCLK
0x0 OMUX block reset synchronous to DOTCLK
0x0 APC block reset synchronous to DOTCLK
0x0 OSD block reset synchronous to DOTCLK
0x0 GAMMA block reset synchronous to
DOTCLK
0x0 OSQ block reset synchronous to DOTCLK
0x0 SCALE block reset synchronous to DOTCLK
2.2 FM Frequency Synthesizer
The FM frequency synthesizer creates a clock equivalent to up to eight times the crystal input clock,
using a digital frequency synthesizer. The modulation period and amplitude are directly controlled
by I2C registers. The I2C interface runs in the LLK_CTRL clock domain, which must be active for
access.
The output frequency (fOUT) is related to the 32-bit PHASE_RATE and crystal frequency (fXCLK) as
follows:
fOUT = fXCLK x 227+NDIV / PHASE_RATE
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